arch/arm/boot/dts/nxp/imx/imx6qdl-sr-som.dtsi

Source file repositories/reference/linux-study-clean/arch/arm/boot/dts/nxp/imx/imx6qdl-sr-som.dtsi

File Facts

System
Linux kernel
Corpus path
arch/arm/boot/dts/nxp/imx/imx6qdl-sr-som.dtsi
Extension
.dtsi
Size
5184 bytes
Lines
157
Domain
Architecture Layer
Bucket
arch/arm
Inferred role
Architecture Layer: configuration, schema, or hardware description
Status
atlas-only

Why This File Exists

CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.

Dependency Surface

Detected Declarations

Annotated Snippet

#include <dt-bindings/gpio/gpio.h>

/ {
	vcc_3v3: regulator-vcc-3v3 {
		compatible = "regulator-fixed";
		regulator-always-on;
		regulator-name = "vcc_3v3";
		regulator-min-microvolt = <3300000>;
		regulator-max-microvolt = <3300000>;
	};
};

&fec {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_microsom_enet_ar8035>;
	phy-mode = "rgmii-id";

	/*
	 * The PHY seems to require a long-enough reset duration to avoid
	 * some rare issues where the PHY gets stuck in an inconsistent and
	 * non-functional state at boot-up. 10ms proved to be fine .
	 */
	phy-reset-duration = <10>;
	phy-reset-gpios = <&gpio4 15 GPIO_ACTIVE_LOW>;
	status = "okay";

	mdio {
		#address-cells = <1>;
		#size-cells = <0>;

		/*
		 * The PHY can appear at either address 0 or 4 due to the
		 * configuration (LED) pin not being pulled sufficiently.
		 */
		ethernet-phy@0 {
			reg = <0>;
			qca,clk-out-frequency = <125000000>;
			qca,smarteee-tw-us-1g = <24>;
		};

		ethernet-phy@4 {
			reg = <4>;
			qca,clk-out-frequency = <125000000>;
			qca,smarteee-tw-us-1g = <24>;
		};

		/*
		 * ADIN1300 (som rev 1.9 or later) is always at address 1. It
		 * will be enabled automatically by U-Boot if detected.
		 */
		ethernet-phy@1 {
			reg = <1>;
			adi,phy-output-clock = "125mhz-free-running";
			status = "disabled";
		};
	};
};

&iomuxc {
	pinctrl_microsom_enet_ar8035: microsom-enet-ar8035grp {
		fsl,pins = <
			MX6QDL_PAD_ENET_MDIO__ENET_MDIO		0x1b8b0
			MX6QDL_PAD_ENET_MDC__ENET_MDC		0x1b0b0
			/* AR8035 reset */
			MX6QDL_PAD_KEY_ROW4__GPIO4_IO15		0x130b0
			/* AR8035 interrupt */
			MX6QDL_PAD_DI0_PIN2__GPIO4_IO18		0x1b0b0
			/* GPIO16 -> AR8035 25MHz */
			MX6QDL_PAD_GPIO_16__ENET_REF_CLK	0x4001b0b0
			MX6QDL_PAD_RGMII_TXC__RGMII_TXC		0x13030

Annotation

Implementation Notes