arch/arm/boot/dts/nxp/imx/imx6ul-tqma6ul1.dtsi
Source file repositories/reference/linux-study-clean/arch/arm/boot/dts/nxp/imx/imx6ul-tqma6ul1.dtsi
File Facts
- System
- Linux kernel
- Corpus path
arch/arm/boot/dts/nxp/imx/imx6ul-tqma6ul1.dtsi- Extension
.dtsi- Size
- 594 bytes
- Lines
- 36
- Domain
- Architecture Layer
- Bucket
- arch/arm
- Inferred role
- Architecture Layer: configuration, schema, or hardware description
- Status
- atlas-only
Why This File Exists
CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.
- CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.
Dependency Surface
- No C-style include directives detected by the generator.
Detected Declarations
- No top-level syscall, struct, function, initcall, or export declaration detected by the generator.
Annotated Snippet
// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT)
/*
* Copyright 2018-2022 TQ-Systems GmbH
* Author: Markus Niebel <Markus.Niebel@tq-group.com>
*/
/ {
model = "TQ-Systems TQMa6UL1 SoM";
compatible = "tq,imx6ul-tqma6ul1", "fsl,imx6ul";
};
/*
* There are no module specific differences compared to TQMa6UL2,
* only external interfaces differ
*/
/*
* Devices not available on i.MX6ULG1 and should not be enabled on
* mainboard level (again)
*/
&can2 {
status = "disabled";
};
&csi {
status = "disabled";
};
&fec2 {
status = "disabled";
};
&lcdif {
status = "disabled";
};
Annotation
- Atlas domain: Architecture Layer / arch/arm.
- Implementation status: atlas-only.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.