arch/arm/boot/dts/nxp/imx/imx6ul-tqma6ul1-mba6ulx.dts
Source file repositories/reference/linux-study-clean/arch/arm/boot/dts/nxp/imx/imx6ul-tqma6ul1-mba6ulx.dts
File Facts
- System
- Linux kernel
- Corpus path
arch/arm/boot/dts/nxp/imx/imx6ul-tqma6ul1-mba6ulx.dts- Extension
.dts- Size
- 1071 bytes
- Lines
- 57
- Domain
- Architecture Layer
- Bucket
- arch/arm
- Inferred role
- Architecture Layer: configuration, schema, or hardware description
- Status
- atlas-only
Why This File Exists
CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.
- CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.
Dependency Surface
imx6ul-tqma6ul2.dtsimba6ulx.dtsiimx6ul-tqma6ul1.dtsi
Detected Declarations
- No top-level syscall, struct, function, initcall, or export declaration detected by the generator.
Annotated Snippet
// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT)
/*
* Copyright 2018-2022 TQ-Systems GmbH
* Author: Markus Niebel <Markus.Niebel@tq-group.com>
*/
/dts-v1/;
#include "imx6ul-tqma6ul2.dtsi"
#include "mba6ulx.dtsi"
#include "imx6ul-tqma6ul1.dtsi"
/ {
model = "TQ-Systems TQMa6UL1 SoM on MBa6ULx board";
compatible = "tq,imx6ul-tqma6ul1-mba6ulx", "tq,imx6ul-tqma6ul1", "fsl,imx6ul";
};
/*
* Note: can2 and fec2 are enabled on mba6ulx level (for i.MX6ULG2 usage)
* and need to be disabled here again
*/
&can2 {
status = "disabled";
};
&fec1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_enet1>, <&pinctrl_enet1_mdc>;
status = "okay";
mdio {
#address-cells = <1>;
#size-cells = <0>;
ethphy0: ethernet-phy@0 {
compatible = "ethernet-phy-ieee802.3-c22";
max-speed = <100>;
reg = <0>;
};
};
};
&fec2 {
/delete-property/ phy-handle;
/delete-node/ mdio;
};
&iomuxc {
pinctrl_enet1_mdc: enet1mdcgrp {
fsl,pins = <
/* mdio */
MX6UL_PAD_GPIO1_IO07__ENET1_MDC 0x1b0b0
MX6UL_PAD_GPIO1_IO06__ENET1_MDIO 0x1b0b0
>;
};
};
Annotation
- Immediate include surface: `imx6ul-tqma6ul2.dtsi`, `mba6ulx.dtsi`, `imx6ul-tqma6ul1.dtsi`.
- Atlas domain: Architecture Layer / arch/arm.
- Implementation status: atlas-only.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.