arch/arm/boot/dts/nxp/imx/imx6ul-tqma6ul2l.dtsi

File Facts

System

Linux kernel

Corpus path

arch/arm/boot/dts/nxp/imx/imx6ul-tqma6ul2l.dtsi

Extension

.dtsi

Size

2266 bytes

Lines

73

Domain

Architecture Layer

Bucket

arch/arm

Inferred role

Architecture Layer: configuration, schema, or hardware description

Status

atlas-only

Why This File Exists

CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.

• CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.

Dependency Surface

• imx6ul.dtsi
• imx6ul-tqma6ul-common.dtsi
• imx6ul-tqma6ulxl-common.dtsi

Detected Declarations

• No top-level syscall, struct, function, initcall, or export declaration detected by the generator.

Annotated Snippet

// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT)
/*
 * Copyright 2018-2022 TQ-Systems GmbH
 * Author: Markus Niebel <Markus.Niebel@tq-group.com>
 */

#include "imx6ul.dtsi"
#include "imx6ul-tqma6ul-common.dtsi"
#include "imx6ul-tqma6ulxl-common.dtsi"

/ {
	model = "TQ-Systems TQMa6UL2L SoM";
	compatible = "tq,imx6ul-tqma6ul2l", "fsl,imx6ul";
};

&usdhc2 {
	fsl,tuning-step = <6>;
};

&iomuxc {
	pinctrl_usdhc2: usdhc2grp {
		fsl,pins = <
			MX6UL_PAD_NAND_RE_B__USDHC2_CLK		0x00017051
			MX6UL_PAD_NAND_WE_B__USDHC2_CMD		0x00017051
			MX6UL_PAD_NAND_DATA00__USDHC2_DATA0	0x00017051
			MX6UL_PAD_NAND_DATA01__USDHC2_DATA1	0x00017051
			MX6UL_PAD_NAND_DATA02__USDHC2_DATA2	0x00017051
			MX6UL_PAD_NAND_DATA03__USDHC2_DATA3	0x00017051
			MX6UL_PAD_NAND_DATA04__USDHC2_DATA4	0x00017051
			MX6UL_PAD_NAND_DATA05__USDHC2_DATA5	0x00017051
			MX6UL_PAD_NAND_DATA06__USDHC2_DATA6	0x00017051
			MX6UL_PAD_NAND_DATA07__USDHC2_DATA7	0x00017051
			/* rst */
			MX6UL_PAD_NAND_ALE__GPIO4_IO10		0x0001b051
		>;
		bootph-all;
	};

	pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
		fsl,pins = <
			MX6UL_PAD_NAND_RE_B__USDHC2_CLK		0x000170e1
			MX6UL_PAD_NAND_WE_B__USDHC2_CMD		0x000170f1
			MX6UL_PAD_NAND_DATA00__USDHC2_DATA0	0x000170f1
			MX6UL_PAD_NAND_DATA01__USDHC2_DATA1	0x000170f1
			MX6UL_PAD_NAND_DATA02__USDHC2_DATA2	0x000170f1
			MX6UL_PAD_NAND_DATA03__USDHC2_DATA3	0x000170f1
			MX6UL_PAD_NAND_DATA04__USDHC2_DATA4	0x000170f1
			MX6UL_PAD_NAND_DATA05__USDHC2_DATA5	0x000170f1
			MX6UL_PAD_NAND_DATA06__USDHC2_DATA6	0x000170f1
			MX6UL_PAD_NAND_DATA07__USDHC2_DATA7	0x000170f1
			/* rst */
			MX6UL_PAD_NAND_ALE__GPIO4_IO10		0x0001b051
		>;
	};

	pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
		fsl,pins = <
			MX6UL_PAD_NAND_RE_B__USDHC2_CLK		0x000170f9
			MX6UL_PAD_NAND_WE_B__USDHC2_CMD		0x000170f1
			MX6UL_PAD_NAND_DATA00__USDHC2_DATA0	0x000170f1
			MX6UL_PAD_NAND_DATA01__USDHC2_DATA1	0x000170f1
			MX6UL_PAD_NAND_DATA02__USDHC2_DATA2	0x000170f1
			MX6UL_PAD_NAND_DATA03__USDHC2_DATA3	0x000170f1
			MX6UL_PAD_NAND_DATA04__USDHC2_DATA4	0x000170f1
			MX6UL_PAD_NAND_DATA05__USDHC2_DATA5	0x000170f1
			MX6UL_PAD_NAND_DATA06__USDHC2_DATA6	0x000170f1
			MX6UL_PAD_NAND_DATA07__USDHC2_DATA7	0x000170f1
			/* rst */
			MX6UL_PAD_NAND_ALE__GPIO4_IO10		0x0001b051
		>;

Annotation

• Immediate include surface: `imx6ul.dtsi`, `imx6ul-tqma6ul-common.dtsi`, `imx6ul-tqma6ulxl-common.dtsi`.
• Atlas domain: Architecture Layer / arch/arm.
• Implementation status: atlas-only.

Implementation Notes

• This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
• Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
• Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.