arch/arm/boot/dts/nxp/imx/imx6ul-var-som-common.dtsi

Source file repositories/reference/linux-study-clean/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-common.dtsi

File Facts

System
Linux kernel
Corpus path
arch/arm/boot/dts/nxp/imx/imx6ul-var-som-common.dtsi
Extension
.dtsi
Size
4898 bytes
Lines
188
Domain
Architecture Layer
Bucket
arch/arm
Inferred role
Architecture Layer: configuration, schema, or hardware description
Status
atlas-only

Why This File Exists

CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.

Dependency Surface

Detected Declarations

Annotated Snippet

// SPDX-License-Identifier: GPL-2.0+
/*
 * Support for the common parts shared by all the different CPU options on
 * Variscite VAR-SOM-6UL Module
 *
 * Copyright 2019 Variscite Ltd.
 * Copyright 2025 Bootlin
 */

#include <dt-bindings/clock/imx6ul-clock.h>
#include <dt-bindings/gpio/gpio.h>

/ {
	model = "Variscite VAR-SOM-6UL module";
	compatible = "variscite,var-som-imx6ul", "fsl,imx6ul";

	memory@80000000 {
		device_type = "memory";
		reg = <0x80000000 0x20000000>;
	};

	reg_3p3v: regulator-3p3v {
		compatible = "regulator-fixed";
		regulator-name = "3P3V";
		regulator-min-microvolt = <3300000>;
		regulator-max-microvolt = <3300000>;
		regulator-always-on;
	};

	reg_gpio_dvfs: reg-gpio-dvfs {
		compatible = "regulator-gpio";
		regulator-min-microvolt = <1300000>;
		regulator-max-microvolt = <1400000>;
		regulator-name = "gpio_dvfs";
		regulator-type = "voltage";
		gpios = <&gpio4 13 GPIO_ACTIVE_HIGH>;
		states = <1300000 0x1
			  1400000 0x0>;
	};
};

&clks {
	assigned-clocks = <&clks IMX6UL_CLK_PLL4_AUDIO_DIV>;
	assigned-clock-rates = <786432000>;
};

&iomuxc {
	pinctrl_i2c1: i2c1grp {
		fsl,pins = <
			MX6UL_PAD_CSI_PIXCLK__I2C1_SCL		0x4001b8b0
			MX6UL_PAD_CSI_MCLK__I2C1_SDA		0x4001b8b0
		>;
	};

	pinctrl_tsc: tscgrp {
		fsl,pins = <
			MX6UL_PAD_GPIO1_IO01__GPIO1_IO01	0xb0
			MX6UL_PAD_GPIO1_IO02__GPIO1_IO02	0xb0
			MX6UL_PAD_GPIO1_IO03__GPIO1_IO03	0xb0
			MX6UL_PAD_GPIO1_IO04__GPIO1_IO04	0xb0
		>;
	};

	pinctrl_uart2: uart2grp {
		fsl,pins = <
			MX6UL_PAD_UART2_TX_DATA__UART2_DCE_TX	0x1b0b1
			MX6UL_PAD_UART2_RX_DATA__UART2_DCE_RX	0x1b0b1
			MX6UL_PAD_UART2_CTS_B__UART2_DCE_CTS	0x1b0b1
			MX6UL_PAD_UART2_RTS_B__UART2_DCE_RTS	0x1b0b1
		>;

Annotation

Implementation Notes