arch/arm/boot/dts/nxp/imx/imx6ul-var-som-enet1.dtsi

Source file repositories/reference/linux-study-clean/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-enet1.dtsi

File Facts

System
Linux kernel
Corpus path
arch/arm/boot/dts/nxp/imx/imx6ul-var-som-enet1.dtsi
Extension
.dtsi
Size
1166 bytes
Lines
45
Domain
Architecture Layer
Bucket
arch/arm
Inferred role
Architecture Layer: configuration, schema, or hardware description
Status
atlas-only

Why This File Exists

CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.

Dependency Surface

Detected Declarations

Annotated Snippet

// SPDX-License-Identifier: GPL-2.0+
/*
 * Ethernet ENET1 support for Variscite VAR-SOM-6UL module with
 * the EC configuration option ((ethernet PHY assembled on SOM).
 *
 * Copyright 2019-2024 Variscite Ltd.
 * Copyright 2026 Dimonoff
 */

&fec1 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_enet1>, <&pinctrl_enet1_gpio>;
	phy-mode = "rmii";
	phy-handle = <&ethphy0>;
	status = "okay";
};

&iomuxc {
	pinctrl_enet1: enet1grp {
		fsl,pins = <
			MX6UL_PAD_ENET1_RX_EN__ENET1_RX_EN	0x1b0b0
			MX6UL_PAD_ENET1_RX_ER__ENET1_RX_ER	0x1b0b0
			MX6UL_PAD_ENET1_RX_DATA0__ENET1_RDATA00	0x1b0b0
			MX6UL_PAD_ENET1_RX_DATA1__ENET1_RDATA01	0x1b0b0
			MX6UL_PAD_ENET1_TX_EN__ENET1_TX_EN	0x1b0b0
			MX6UL_PAD_ENET1_TX_DATA0__ENET1_TDATA00	0x1b0b0
			MX6UL_PAD_ENET1_TX_DATA1__ENET1_TDATA01	0x1b0b0
			MX6UL_PAD_ENET1_TX_CLK__ENET1_REF_CLK1	0x4001b031
		>;
	};
};

&mdio_enet2 {
	ethphy0: ethernet-phy@1 {
		compatible = "ethernet-phy-ieee802.3-c22";
		reg = <1>;
		clocks = <&rmii_ref_clk>;
		clock-names = "rmii-ref";
		reset-gpios = <&gpio5 0 GPIO_ACTIVE_LOW>;
		reset-assert-us = <100000>;
		micrel,led-mode = <1>;
		micrel,rmii-reference-clock-select-25-mhz;
	};
};

Annotation

Implementation Notes