arch/arm/boot/dts/nxp/imx/imx6ul-var-som-wifi.dtsi
Source file repositories/reference/linux-study-clean/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-wifi.dtsi
File Facts
- System
- Linux kernel
- Corpus path
arch/arm/boot/dts/nxp/imx/imx6ul-var-som-wifi.dtsi- Extension
.dtsi- Size
- 1767 bytes
- Lines
- 76
- Domain
- Architecture Layer
- Bucket
- arch/arm
- Inferred role
- Architecture Layer: configuration, schema, or hardware description
- Status
- atlas-only
Why This File Exists
CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.
- CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.
Dependency Surface
- No C-style include directives detected by the generator.
Detected Declarations
- No top-level syscall, struct, function, initcall, or export declaration detected by the generator.
Annotated Snippet
// SPDX-License-Identifier: GPL-2.0+
/*
* Support optional Wifi/Bluetooth on Variscite VAR-SOM-6UL module.
*
* Copyright 2019-2024 Variscite Ltd.
* Copyright 2026 Dimonoff
*/
/ {
reg_sd1_vmmc: regulator_sd1_vmmc {
compatible = "regulator-fixed";
regulator-name = "VMMC1";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
gpio = <&gpio5 2 GPIO_ACTIVE_HIGH>;
enable-active-high;
startup-delay-us = <10000>;
};
usdhc1_pwrseq: usdhc1-pwrseq {
compatible = "mmc-pwrseq-simple";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_brcm_wifi>;
reset-gpios = <&gpio5 6 GPIO_ACTIVE_LOW>;
};
};
&iomuxc {
pinctrl_32k_clk: 32kclkgrp {
/*
* For TP option, an additional oscillator is assembled on the
* SOM to provide 32 kHz to the WiFi module. Without TP option,
* this pin is configured to provide the 32 KHz clock to the
* WiFi module.
*/
fsl,pins = <
MX6UL_PAD_GPIO1_IO03__OSC32K_32K_OUT 0x03029
>;
};
};
&tsc {
status = "disabled";
};
/* Bluetooth UART */
&uart2 {
bluetooth {
compatible = "brcm,bcm43438-bt";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_brcm_bt>;
shutdown-gpios = <&gpio5 4 GPIO_ACTIVE_HIGH>;
vbat-supply = <®_3p3v>;
vddio-supply = <®_3p3v>;
};
};
&usdhc1 {
#address-cells = <1>;
#size-cells = <0>;
pinctrl-names = "default", "state_100mhz", "state_200mhz";
pinctrl-0 = <&pinctrl_usdhc1>, <&pinctrl_32k_clk>;
pinctrl-1 = <&pinctrl_usdhc1_100mhz>, <&pinctrl_32k_clk>;
pinctrl-2 = <&pinctrl_usdhc1_200mhz>, <&pinctrl_32k_clk>;
no-1-8-v;
non-removable;
mmc-pwrseq = <&usdhc1_pwrseq>;
vmmc-supply = <®_sd1_vmmc>;
status = "okay";
Annotation
- Atlas domain: Architecture Layer / arch/arm.
- Implementation status: atlas-only.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.