arch/arm/boot/dts/nxp/imx/imx6ull-colibri-iris-v2.dtsi
Source file repositories/reference/linux-study-clean/arch/arm/boot/dts/nxp/imx/imx6ull-colibri-iris-v2.dtsi
File Facts
- System
- Linux kernel
- Corpus path
arch/arm/boot/dts/nxp/imx/imx6ull-colibri-iris-v2.dtsi- Extension
.dtsi- Size
- 565 bytes
- Lines
- 28
- Domain
- Architecture Layer
- Bucket
- arch/arm
- Inferred role
- Architecture Layer: configuration, schema, or hardware description
- Status
- atlas-only
Why This File Exists
CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.
- CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.
Dependency Surface
imx6ull-colibri-iris.dtsi
Detected Declarations
- No top-level syscall, struct, function, initcall, or export declaration detected by the generator.
Annotated Snippet
// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
/*
* Copyright 2018-2022 Toradex
*/
#include "imx6ull-colibri-iris.dtsi"
/ {
reg_3v3_vmmc: regulator-3v3-vmmc {
compatible = "regulator-fixed";
regulator-name = "3v3_vmmc";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
gpio = <&gpio1 26 GPIO_ACTIVE_HIGH>;
startup-delay-us = <100>;
enable-active-high;
};
};
&usdhc1 {
cap-power-off-card;
vmmc-supply = <®_3v3_vmmc>;
/delete-property/ keep-power-in-suspend;
/delete-property/ no-1-8-v;
status = "okay";
};
Annotation
- Immediate include surface: `imx6ull-colibri-iris.dtsi`.
- Atlas domain: Architecture Layer / arch/arm.
- Implementation status: atlas-only.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.