arch/arm/boot/dts/nxp/imx/imx6ull-dhcom-drc02.dts

Source file repositories/reference/linux-study-clean/arch/arm/boot/dts/nxp/imx/imx6ull-dhcom-drc02.dts

File Facts

System
Linux kernel
Corpus path
arch/arm/boot/dts/nxp/imx/imx6ull-dhcom-drc02.dts
Extension
.dts
Size
2288 bytes
Lines
100
Domain
Architecture Layer
Bucket
arch/arm
Inferred role
Architecture Layer: configuration, schema, or hardware description
Status
atlas-only

Why This File Exists

CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.

Dependency Surface

Detected Declarations

Annotated Snippet

// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
/*
 * Copyright (C) 2023 DH electronics GmbH
 *
 * DHCOM iMX6ULL variant:
 * DHCM-iMX6ULL-C080-R051-F0409-SPI-E2-CAN2-SD-RTC-ADC-I-01D2
 * DHCOR PCB number: 578-200 or newer
 * DHCOM PCB number: 579-200 or newer
 * DRC02 PCB number: 568-100 or newer (2nd ethernet by SoM)
 */
/dts-v1/;

#include "imx6ull-dhcom-som.dtsi"
#include "imx6ull-dhcom-som-cfg-sdcard.dtsi"

/ {
	model = "DH electronics i.MX6ULL DHCOM on DRC02";
	compatible = "dh,imx6ull-dhcom-drc02", "dh,imx6ull-dhcom-som",
		     "dh,imx6ull-dhcor-som", "fsl,imx6ull";
};

/*
 * The signals for CAN2 TX and RX are routed to the DHCOM UART1 RTS/CTS pins.
 * Therefore the UART RTS/CTS must be output on other DHCOM pins, see uart1
 * node below.
 */
&can2 {
	status = "okay";
};

&gpio1 {
	gpio-line-names =
		"", "", "", "",
		"", "", "", "",
		"", "", "", "DRC02-In2",
		"", "", "", "",
		"", "", "DHCOM-I", "",
		"", "", "", "",
		"", "", "", "",
		"", "", "", "";
};

&gpio4 {
	gpio-line-names =
		"", "", "", "",
		"", "", "", "",
		"", "", "", "",
		"", "", "", "",
		"", "DRC02-HW0", "DRC02-HW1", "DHCOM-M",
		"DRC02-HW2", "DHCOM-U", "DHCOM-T", "DHCOM-S",
		"DHCOM-R", "DHCOM-Q", "DHCOM-P", "DHCOM-O",
		"DHCOM-N", "", "", "";
	/*
	 * NOTE: On DRC02, the RS485_RX_En is controlled by a separate
	 * GPIO line, however the i.MX6ULL UART driver assumes RX happens
	 * during TX anyway and that it only controls drive enable DE
	 * line. Hence, the RX is always enabled here.
	 */
	rs485-rx-en-hog {
		gpio-hog;
		gpios = <25 0>; /* GPIO Q */
		line-name = "rs485-rx-en";
		output-low;
	};
};

&gpio5 {
	gpio-line-names =
		"DHCOM-A", "DHCOM-B", "DHCOM-C", "DRC02-Out2",
		"DHCOM-E", "", "", "DRC02-Out1",

Annotation

Implementation Notes