arch/arm/boot/dts/nxp/imx/imx6ull-dhcor-som.dtsi

Source file repositories/reference/linux-study-clean/arch/arm/boot/dts/nxp/imx/imx6ull-dhcor-som.dtsi

File Facts

System
Linux kernel
Corpus path
arch/arm/boot/dts/nxp/imx/imx6ull-dhcor-som.dtsi
Extension
.dtsi
Size
6969 bytes
Lines
271
Domain
Architecture Layer
Bucket
arch/arm
Inferred role
Architecture Layer: configuration, schema, or hardware description
Status
atlas-only

Why This File Exists

CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.

Dependency Surface

Detected Declarations

Annotated Snippet

// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
/*
 * Copyright (C) 2023 DH electronics GmbH
 */

#include <dt-bindings/clock/imx6ul-clock.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
#include <dt-bindings/leds/common.h>
#include <dt-bindings/pwm/pwm.h>
#include <dt-bindings/regulator/dlg,da9063-regulator.h>
#include "imx6ull.dtsi"

/ {
	aliases {
		/delete-property/ mmc0;
		/delete-property/ mmc1;
	};

	memory@80000000 {
		/* Appropriate memory size will be filled by U-Boot */
		reg = <0x80000000 0>;
		device_type = "memory";
	};
};

&cpu0 {
	/*
	 * Due to the design as a solderable SOM, there are no capacitors
	 * below the SoC, therefore higher voltages are required.
	 * Due to CPU lifetime consideration of the SoC manufacturer and
	 * the preferred area of operation in the industrial related
	 * environment, set the maximum frequency for each DHCOM i.MX6ULL
	 * to 792MHz, as with the industrial type.
	 */
	clock-frequency = <792000000>;
	operating-points = <
		/* kHz	uV */
		792000	1250000 /* Voltage increased */
		528000	1175000
		396000	1025000
		198000	950000
	>;
	fsl,soc-operating-points = <
		/* KHz	uV */
		792000	1250000 /* Voltage increased */
		528000	1175000
		396000	1175000
		198000	1175000
	>;
};

&gpio1 {
	pinctrl-0 = <&pinctrl_spi1_switch>;
	pinctrl-names = "default";
	/*
	 * Pin SPI_BOOT_FLASH_EN (GPIO 1.9) is a switch for either using the
	 * DHCOM SPI1 interface or accessing the SPI bootflash. Both using
	 * ecspi1, but muxed to different pins. The DHCOM SPI1 interface uses
	 * the pins PAD_LCD_DATA21..23 and the SPI bootflash uses the pins
	 * PAD_CSI_DATA04..07. If the SPI bootflash is enabled the pins for
	 * DHCOM GPIOs N/O/P/Q/R/S/T/U aren't usable anymore, because they
	 * are used for the bus interface to the SPI bootflash. The GPIOs are
	 * disconnected by a buffer which is also controlled via the pin
	 * SPI_BOOT_FLASH_EN. Therefore the access to the bootflash is a
	 * special case and is disabled by setting GPIO 1.9 to high.
	 */
	spi1-switch-hog {
		gpio-hog;
		gpios = <9 0>;

Annotation

Implementation Notes