arch/arm/boot/dts/nxp/imx/imx6ull-phytec-segin.dtsi

File Facts

System

Linux kernel

Corpus path

arch/arm/boot/dts/nxp/imx/imx6ull-phytec-segin.dtsi

Extension

.dtsi

Size

625 bytes

Lines

32

Domain

Architecture Layer

Bucket

arch/arm

Inferred role

Architecture Layer: configuration, schema, or hardware description

Status

atlas-only

Why This File Exists

CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.

• CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.

Dependency Surface

• imx6ul-phytec-segin.dtsi

Detected Declarations

• No top-level syscall, struct, function, initcall, or export declaration detected by the generator.

Annotated Snippet

// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
 * Copyright (C) 2019 PHYTEC Messtechnik GmbH
 * Author: Stefan Riedmueller <s.riedmueller@phytec.de>
 */

#include "imx6ul-phytec-segin.dtsi"

/ {
	model = "PHYTEC phyBOARD-Segin i.MX6 ULL";
	compatible = "phytec,imx6ull-pbacd-10", "phytec,imx6ull-pcl063","fsl,imx6ull";
};

&iomuxc {
	/delete-node/ flexcan1engrp;
	/delete-node/ rtcintgrp;
};

&iomuxc_snvs {
	princtrl_flexcan1_en: flexcan1engrp {
		fsl,pins = <
			MX6ULL_PAD_SNVS_TAMPER2__GPIO5_IO02	0x17059
		>;
	};

	pinctrl_rtc_int: rtcintgrp {
		fsl,pins = <
			MX6ULL_PAD_SNVS_TAMPER1__GPIO5_IO01	0x17059
		>;
	};
};

Annotation

• Immediate include surface: `imx6ul-phytec-segin.dtsi`.
• Atlas domain: Architecture Layer / arch/arm.
• Implementation status: atlas-only.

Implementation Notes

• This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
• Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
• Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.