arch/arm/boot/dts/nxp/imx/imx6ull-phytec-segin-peb-av-02.dtsi
Source file repositories/reference/linux-study-clean/arch/arm/boot/dts/nxp/imx/imx6ull-phytec-segin-peb-av-02.dtsi
File Facts
- System
- Linux kernel
- Corpus path
arch/arm/boot/dts/nxp/imx/imx6ull-phytec-segin-peb-av-02.dtsi- Extension
.dtsi- Size
- 503 bytes
- Lines
- 27
- Domain
- Architecture Layer
- Bucket
- arch/arm
- Inferred role
- Architecture Layer: configuration, schema, or hardware description
- Status
- atlas-only
Why This File Exists
CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.
- CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.
Dependency Surface
imx6ul-phytec-segin-peb-av-02.dtsi
Detected Declarations
- No top-level syscall, struct, function, initcall, or export declaration detected by the generator.
Annotated Snippet
// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT)
/*
* Copyright (C) 2018 PHYTEC Messtechnik GmbH
* Author: Stefan Riedmueller <s.riedmueller@phytec.de>
*/
#include "imx6ul-phytec-segin-peb-av-02.dtsi"
&iomuxc {
/delete-node/ edtft5406grp;
/delete-node/ stmpegrp;
};
&iomuxc_snvs {
pinctrl_edt_ft5406: edtft5406grp {
fsl,pins = <
MX6ULL_PAD_SNVS_TAMPER5__GPIO5_IO05 0x1b0b0
>;
};
pinctrl_stmpe: stmpegrp {
fsl,pins = <
MX6ULL_PAD_SNVS_TAMPER3__GPIO5_IO03 0x17059
>;
};
};
Annotation
- Immediate include surface: `imx6ul-phytec-segin-peb-av-02.dtsi`.
- Atlas domain: Architecture Layer / arch/arm.
- Implementation status: atlas-only.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.