arch/arm/boot/dts/nxp/imx/imx6ull-tarragon-slave.dts

File Facts

System

Linux kernel

Corpus path

arch/arm/boot/dts/nxp/imx/imx6ull-tarragon-slave.dts

Extension

.dts

Size

641 bytes

Lines

33

Domain

Architecture Layer

Bucket

arch/arm

Inferred role

Architecture Layer: configuration, schema, or hardware description

Status

atlas-only

Why This File Exists

CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.

• CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.

Dependency Surface

• imx6ull-tarragon-common.dtsi

Detected Declarations

• No top-level syscall, struct, function, initcall, or export declaration detected by the generator.

Annotated Snippet

// SPDX-License-Identifier: GPL-2.0 OR MIT
//
// Copyright (C) 2023 chargebyte GmbH

#include "imx6ull-tarragon-common.dtsi"

/ {
	model = "chargebyte Tarragon Slave";
	compatible = "chargebyte,imx6ull-tarragon-slave", "fsl,imx6ull";
};

&ecspi2 {
	status = "okay";

	qca700x_cp: ethernet@0 {
		reg = <0x0>;
		compatible = "qca,qca7000";
		pinctrl-names = "default";
		pinctrl-0 = <&pinctrl_qca700x_cp_int
			     &pinctrl_qca700x_cp_rst
			     &pinctrl_qca700x_cp_btld>;
		interrupt-parent = <&gpio2>;
		interrupts = <19 IRQ_TYPE_EDGE_RISING>;
		spi-cpha;
		spi-cpol;
		spi-max-frequency = <12000000>;
	};
};

&fec1 {
	status = "okay";
};

Annotation

• Immediate include surface: `imx6ull-tarragon-common.dtsi`.
• Atlas domain: Architecture Layer / arch/arm.
• Implementation status: atlas-only.

Implementation Notes

• This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
• Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
• Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.