arch/arm/boot/dts/nxp/imx/imx7d-colibri-iris.dts
Source file repositories/reference/linux-study-clean/arch/arm/boot/dts/nxp/imx/imx7d-colibri-iris.dts
File Facts
- System
- Linux kernel
- Corpus path
arch/arm/boot/dts/nxp/imx/imx7d-colibri-iris.dts- Extension
.dts- Size
- 1030 bytes
- Lines
- 58
- Domain
- Architecture Layer
- Bucket
- arch/arm
- Inferred role
- Architecture Layer: configuration, schema, or hardware description
- Status
- atlas-only
Why This File Exists
CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.
- CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.
Dependency Surface
imx7d-colibri.dtsiimx7-colibri-iris.dtsi
Detected Declarations
- No top-level syscall, struct, function, initcall, or export declaration detected by the generator.
Annotated Snippet
// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
/*
* Copyright 2022 Toradex
*/
/dts-v1/;
#include "imx7d-colibri.dtsi"
#include "imx7-colibri-iris.dtsi"
/ {
model = "Toradex Colibri iMX7D on Iris Carrier Board";
compatible = "toradex,colibri-imx7d-iris",
"toradex,colibri-imx7d",
"fsl,imx7d";
};
&ad7879_ts {
status = "okay";
};
/*
* The Atmel maxtouch controller uses SODIMM 28/30, also used for PWM<B>, PWM<C>, aka pwm2, pwm3.
* So if you enable following capacitive touch controller, disable pwm2/pwm3 first.
*/
&atmel_mxt_ts {
status = "disabled";
};
&backlight {
status = "okay";
};
&lcdif {
status = "okay";
};
&panel_dpi {
status = "okay";
};
/* Colibri PWM<B> */
&pwm2 {
/* The pwm2 should be disabled to enable atmel_mxt_ts touchscreen for adapter. */
status = "okay";
};
/* Colibri PWM<C> */
&pwm3 {
/* The pwm3 should be disabled to enable atmel_mxt_ts touchscreen for adapter. */
status = "okay";
};
/* Colibri USBH */
&usbotg2 {
disable-over-current;
status = "okay";
};
Annotation
- Immediate include surface: `imx7d-colibri.dtsi`, `imx7-colibri-iris.dtsi`.
- Atlas domain: Architecture Layer / arch/arm.
- Implementation status: atlas-only.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.