arch/arm/boot/dts/nxp/imx/imx7d-pinfunc.h
Source file repositories/reference/linux-study-clean/arch/arm/boot/dts/nxp/imx/imx7d-pinfunc.h
File Facts
- System
- Linux kernel
- Corpus path
arch/arm/boot/dts/nxp/imx/imx7d-pinfunc.h- Extension
.h- Size
- 108507 bytes
- Lines
- 1155
- Domain
- Architecture Layer
- Bucket
- arch/arm
- Inferred role
- Architecture Layer: implementation source
- Status
- source implementation candidate
Why This File Exists
CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.
- CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.
Dependency Surface
- No C-style include directives detected by the generator.
Detected Declarations
- No top-level syscall, struct, function, initcall, or export declaration detected by the generator.
Annotated Snippet
#ifndef __DTS_IMX7D_PINFUNC_H
#define __DTS_IMX7D_PINFUNC_H
/*
* The pin function ID is a tuple of
* <mux_reg conf_reg input_reg mux_mode input_val>
*/
#define MX7D_PAD_LPSR_GPIO1_IO00__GPIO1_IO0 0x0000 0x0030 0x0000 0x0 0x0
#define MX7D_PAD_LPSR_GPIO1_IO00__PWM4_OUT 0x0000 0x0030 0x0000 0x1 0x0
#define MX7D_PAD_LPSR_GPIO1_IO00__WDOG1_WDOG_ANY 0x0000 0x0030 0x0000 0x2 0x0
#define MX7D_PAD_LPSR_GPIO1_IO00__WDOG1_WDOG_B 0x0000 0x0030 0x0000 0x3 0x0
#define MX7D_PAD_LPSR_GPIO1_IO00__WDOG1_WDOG__RST_B_DEB 0x0000 0x0030 0x0000 0x4 0x0
#define MX7D_PAD_LPSR_GPIO1_IO01__GPIO1_IO1 0x0004 0x0034 0x0000 0x0 0x0
#define MX7D_PAD_LPSR_GPIO1_IO01__PWM1_OUT 0x0004 0x0034 0x0000 0x1 0x0
#define MX7D_PAD_LPSR_GPIO1_IO01__CCM_ENET_REF_CLK3 0x0004 0x0034 0x0000 0x2 0x0
#define MX7D_PAD_LPSR_GPIO1_IO01__SAI1_MCLK 0x0004 0x0034 0x0000 0x3 0x0
#define MX7D_PAD_LPSR_GPIO1_IO01__ANATOP_24M_OUT 0x0004 0x0034 0x0000 0x4 0x0
#define MX7D_PAD_LPSR_GPIO1_IO01__OBSERVE0_OUT 0x0004 0x0034 0x0000 0x6 0x0
#define MX7D_PAD_LPSR_GPIO1_IO02__GPIO1_IO2 0x0008 0x0038 0x0000 0x0 0x0
#define MX7D_PAD_LPSR_GPIO1_IO02__PWM2_OUT 0x0008 0x0038 0x0000 0x1 0x0
#define MX7D_PAD_LPSR_GPIO1_IO02__CCM_ENET_REF_CLK1 0x0008 0x0038 0x0564 0x2 0x3
#define MX7D_PAD_LPSR_GPIO1_IO02__SAI2_MCLK 0x0008 0x0038 0x0000 0x3 0x0
#define MX7D_PAD_LPSR_GPIO1_IO02__CCM_CLKO1 0x0008 0x0038 0x0000 0x5 0x0
#define MX7D_PAD_LPSR_GPIO1_IO02__OBSERVE1_OUT 0x0008 0x0038 0x0000 0x6 0x0
#define MX7D_PAD_LPSR_GPIO1_IO02__USB_OTG1_ID 0x0008 0x0038 0x0734 0x7 0x3
#define MX7D_PAD_LPSR_GPIO1_IO03__GPIO1_IO3 0x000C 0x003C 0x0000 0x0 0x0
#define MX7D_PAD_LPSR_GPIO1_IO03__PWM3_OUT 0x000C 0x003C 0x0000 0x1 0x0
#define MX7D_PAD_LPSR_GPIO1_IO03__CCM_ENET_REF_CLK2 0x000C 0x003C 0x0570 0x2 0x3
#define MX7D_PAD_LPSR_GPIO1_IO03__SAI3_MCLK 0x000C 0x003C 0x0000 0x3 0x0
#define MX7D_PAD_LPSR_GPIO1_IO03__CCM_CLKO2 0x000C 0x003C 0x0000 0x5 0x0
#define MX7D_PAD_LPSR_GPIO1_IO03__OBSERVE2_OUT 0x000C 0x003C 0x0000 0x6 0x0
#define MX7D_PAD_LPSR_GPIO1_IO03__USB_OTG2_ID 0x000C 0x003C 0x0730 0x7 0x3
#define MX7D_PAD_LPSR_GPIO1_IO04__GPIO1_IO4 0x0010 0x0040 0x0000 0x0 0x0
#define MX7D_PAD_LPSR_GPIO1_IO04__USB_OTG1_OC 0x0010 0x0040 0x072C 0x1 0x1
#define MX7D_PAD_LPSR_GPIO1_IO04__FLEXTIMER1_CH4 0x0010 0x0040 0x0594 0x2 0x1
#define MX7D_PAD_LPSR_GPIO1_IO04__UART5_DCE_CTS 0x0010 0x0040 0x0000 0x3 0x0
#define MX7D_PAD_LPSR_GPIO1_IO04__UART5_DTE_RTS 0x0010 0x0040 0x0710 0x3 0x4
#define MX7D_PAD_LPSR_GPIO1_IO04__I2C1_SCL 0x0010 0x0040 0x05D4 0x4 0x2
#define MX7D_PAD_LPSR_GPIO1_IO04__OBSERVE3_OUT 0x0010 0x0040 0x0000 0x6 0x0
#define MX7D_PAD_LPSR_GPIO1_IO05__GPIO1_IO5 0x0014 0x0044 0x0000 0x0 0x0
#define MX7D_PAD_LPSR_GPIO1_IO05__USB_OTG1_PWR 0x0014 0x0044 0x0000 0x1 0x0
#define MX7D_PAD_LPSR_GPIO1_IO05__FLEXTIMER1_CH5 0x0014 0x0044 0x0598 0x2 0x1
#define MX7D_PAD_LPSR_GPIO1_IO05__UART5_DCE_RTS 0x0014 0x0044 0x0710 0x3 0x5
#define MX7D_PAD_LPSR_GPIO1_IO05__UART5_DTE_CTS 0x0014 0x0044 0x0000 0x3 0x0
#define MX7D_PAD_LPSR_GPIO1_IO05__I2C1_SDA 0x0014 0x0044 0x05D8 0x4 0x2
#define MX7D_PAD_LPSR_GPIO1_IO05__OBSERVE4_OUT 0x0014 0x0044 0x0000 0x6 0x0
#define MX7D_PAD_LPSR_GPIO1_IO06__GPIO1_IO6 0x0018 0x0048 0x0000 0x0 0x0
#define MX7D_PAD_LPSR_GPIO1_IO06__USB_OTG2_OC 0x0018 0x0048 0x0728 0x1 0x1
#define MX7D_PAD_LPSR_GPIO1_IO06__FLEXTIMER1_CH6 0x0018 0x0048 0x059C 0x2 0x1
#define MX7D_PAD_LPSR_GPIO1_IO06__UART5_DCE_RX 0x0018 0x0048 0x0714 0x3 0x4
#define MX7D_PAD_LPSR_GPIO1_IO06__UART5_DTE_TX 0x0018 0x0048 0x0000 0x3 0x0
#define MX7D_PAD_LPSR_GPIO1_IO06__I2C2_SCL 0x0018 0x0048 0x05DC 0x4 0x2
#define MX7D_PAD_LPSR_GPIO1_IO06__CCM_WAIT 0x0018 0x0048 0x0000 0x5 0x0
#define MX7D_PAD_LPSR_GPIO1_IO06__KPP_ROW4 0x0018 0x0048 0x0624 0x6 0x1
#define MX7D_PAD_LPSR_GPIO1_IO07__GPIO1_IO7 0x001C 0x004C 0x0000 0x0 0x0
#define MX7D_PAD_LPSR_GPIO1_IO07__USB_OTG2_PWR 0x001C 0x004C 0x0000 0x1 0x0
#define MX7D_PAD_LPSR_GPIO1_IO07__FLEXTIMER1_CH7 0x001C 0x004C 0x05A0 0x2 0x1
#define MX7D_PAD_LPSR_GPIO1_IO07__UART5_DCE_TX 0x001C 0x004C 0x0000 0x3 0x0
#define MX7D_PAD_LPSR_GPIO1_IO07__UART5_DTE_RX 0x001C 0x004C 0x0714 0x3 0x5
#define MX7D_PAD_LPSR_GPIO1_IO07__I2C2_SDA 0x001C 0x004C 0x05E0 0x4 0x2
#define MX7D_PAD_LPSR_GPIO1_IO07__CCM_STOP 0x001C 0x004C 0x0000 0x5 0x0
#define MX7D_PAD_LPSR_GPIO1_IO07__KPP_COL4 0x001C 0x004C 0x0604 0x6 0x1
#define MX7D_PAD_GPIO1_IO08__GPIO1_IO8 0x0014 0x026C 0x0000 0x0 0x0
#define MX7D_PAD_GPIO1_IO08__SD1_VSELECT 0x0014 0x026C 0x0000 0x1 0x0
#define MX7D_PAD_GPIO1_IO08__WDOG1_WDOG_B 0x0014 0x026C 0x0000 0x2 0x0
#define MX7D_PAD_GPIO1_IO08__UART3_DCE_RX 0x0014 0x026C 0x0704 0x3 0x0
#define MX7D_PAD_GPIO1_IO08__UART3_DTE_TX 0x0014 0x026C 0x0000 0x3 0x0
#define MX7D_PAD_GPIO1_IO08__I2C3_SCL 0x0014 0x026C 0x05E4 0x4 0x0
#define MX7D_PAD_GPIO1_IO08__KPP_COL5 0x0014 0x026C 0x0608 0x6 0x0
#define MX7D_PAD_GPIO1_IO08__PWM1_OUT 0x0014 0x026C 0x0000 0x7 0x0
#define MX7D_PAD_GPIO1_IO09__GPIO1_IO9 0x0018 0x0270 0x0000 0x0 0x0
#define MX7D_PAD_GPIO1_IO09__SD1_LCTL 0x0018 0x0270 0x0000 0x1 0x0
#define MX7D_PAD_GPIO1_IO09__CCM_ENET_REF_CLK3 0x0018 0x0270 0x0000 0x2 0x0
#define MX7D_PAD_GPIO1_IO09__UART3_DCE_TX 0x0018 0x0270 0x0000 0x3 0x0
#define MX7D_PAD_GPIO1_IO09__UART3_DTE_RX 0x0018 0x0270 0x0704 0x3 0x1
#define MX7D_PAD_GPIO1_IO09__I2C3_SDA 0x0018 0x0270 0x05E8 0x4 0x0
#define MX7D_PAD_GPIO1_IO09__CCM_PMIC_READY 0x0018 0x0270 0x04F4 0x5 0x0
#define MX7D_PAD_GPIO1_IO09__KPP_ROW5 0x0018 0x0270 0x0628 0x6 0x0
#define MX7D_PAD_GPIO1_IO09__PWM2_OUT 0x0018 0x0270 0x0000 0x7 0x0
#define MX7D_PAD_GPIO1_IO10__GPIO1_IO10 0x001C 0x0274 0x0000 0x0 0x0
#define MX7D_PAD_GPIO1_IO10__SD2_LCTL 0x001C 0x0274 0x0000 0x1 0x0
#define MX7D_PAD_GPIO1_IO10__ENET1_MDIO 0x001C 0x0274 0x0568 0x2 0x0
#define MX7D_PAD_GPIO1_IO10__UART3_DCE_RTS 0x001C 0x0274 0x0700 0x3 0x0
#define MX7D_PAD_GPIO1_IO10__UART3_DTE_CTS 0x001C 0x0274 0x0000 0x3 0x0
#define MX7D_PAD_GPIO1_IO10__I2C4_SCL 0x001C 0x0274 0x05EC 0x4 0x0
#define MX7D_PAD_GPIO1_IO10__FLEXTIMER1_PHA 0x001C 0x0274 0x05A4 0x5 0x0
#define MX7D_PAD_GPIO1_IO10__KPP_COL6 0x001C 0x0274 0x060C 0x6 0x0
#define MX7D_PAD_GPIO1_IO10__PWM3_OUT 0x001C 0x0274 0x0000 0x7 0x0
#define MX7D_PAD_GPIO1_IO11__GPIO1_IO11 0x0020 0x0278 0x0000 0x0 0x0Annotation
- Atlas domain: Architecture Layer / arch/arm.
- Implementation status: source implementation candidate.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.