arch/arm/boot/dts/nxp/imx/imxrt1050.dtsi

Source file repositories/reference/linux-study-clean/arch/arm/boot/dts/nxp/imx/imxrt1050.dtsi

File Facts

System
Linux kernel
Corpus path
arch/arm/boot/dts/nxp/imx/imxrt1050.dtsi
Extension
.dtsi
Size
4048 bytes
Lines
161
Domain
Architecture Layer
Bucket
arch/arm
Inferred role
Architecture Layer: configuration, schema, or hardware description
Status
atlas-only

Why This File Exists

CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.

Dependency Surface

Detected Declarations

Annotated Snippet

// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
 * Copyright (C) 2019
 * Author(s): Giulio Benetti <giulio.benetti@benettiengineering.com>
 */

#include "../../armv7-m.dtsi"
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/clock/imxrt1050-clock.h>
#include <dt-bindings/gpio/gpio.h>

/ {
	#address-cells = <1>;
	#size-cells = <1>;

	clocks {
		osc: osc {
			compatible = "fixed-clock";
			#clock-cells = <0>;
			clock-frequency = <24000000>;
		};

		osc3M: osc3M {
			compatible = "fixed-clock";
			#clock-cells = <0>;
			clock-frequency = <3000000>;
		};
	};

	soc {
		lpuart1: serial@40184000 {
			compatible = "fsl,imxrt1050-lpuart", "fsl,imx7ulp-lpuart";
			reg = <0x40184000 0x4000>;
			interrupts = <20>;
			clocks = <&clks IMXRT1050_CLK_LPUART1>;
			clock-names = "ipg";
			status = "disabled";
		};

		iomuxc: pinctrl@401f8000 {
			compatible = "fsl,imxrt1050-iomuxc";
			reg = <0x401f8000 0x4000>;
			fsl,mux_mask = <0x7>;
		};

		anatop: anatop@400d8000 {
			compatible = "fsl,imxrt-anatop";
			reg = <0x400d8000 0x4000>;
		};

		clks: clock-controller@400fc000 {
			compatible = "fsl,imxrt1050-ccm";
			reg = <0x400fc000 0x4000>;
			interrupts = <95>, <96>;
			clocks = <&osc>;
			clock-names = "osc";
			#clock-cells = <1>;
			assigned-clocks = <&clks IMXRT1050_CLK_PLL1_BYPASS>,
				<&clks IMXRT1050_CLK_PLL1_BYPASS>,
				<&clks IMXRT1050_CLK_PLL2_BYPASS>,
				<&clks IMXRT1050_CLK_PLL3_BYPASS>,
				<&clks IMXRT1050_CLK_PLL3_PFD1_664_62M>,
				<&clks IMXRT1050_CLK_PLL2_PFD2_396M>;
			assigned-clock-parents = <&clks IMXRT1050_CLK_PLL1_REF_SEL>,
				<&clks IMXRT1050_CLK_PLL1_ARM>,
				<&clks IMXRT1050_CLK_PLL2_SYS>,
				<&clks IMXRT1050_CLK_PLL3_USB_OTG>,
				<&clks IMXRT1050_CLK_PLL3_USB_OTG>,
				<&clks IMXRT1050_CLK_PLL2_SYS>;
		};

Annotation

Implementation Notes