arch/arm/boot/dts/nxp/lpc/lpc18xx.dtsi
Source file repositories/reference/linux-study-clean/arch/arm/boot/dts/nxp/lpc/lpc18xx.dtsi
File Facts
- System
- Linux kernel
- Corpus path
arch/arm/boot/dts/nxp/lpc/lpc18xx.dtsi- Extension
.dtsi- Size
- 14411 bytes
- Lines
- 544
- Domain
- Architecture Layer
- Bucket
- arch/arm
- Inferred role
- Architecture Layer: configuration, schema, or hardware description
- Status
- atlas-only
Why This File Exists
CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.
- CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.
Dependency Surface
../../armv7-m.dtsidt-bindings/clock/lpc18xx-cgu.hdt-bindings/clock/lpc18xx-ccu.h
Detected Declarations
- No top-level syscall, struct, function, initcall, or export declaration detected by the generator.
Annotated Snippet
#include "../../armv7-m.dtsi"
#include "dt-bindings/clock/lpc18xx-cgu.h"
#include "dt-bindings/clock/lpc18xx-ccu.h"
#define LPC_PIN(port, pin) (0x##port * 32 + pin)
#define LPC_GPIO(port, pin) (port * 32 + pin)
/ {
#address-cells = <1>;
#size-cells = <1>;
cpus {
#address-cells = <1>;
#size-cells = <0>;
cpu@0 {
compatible = "arm,cortex-m3";
device_type = "cpu";
reg = <0x0>;
clocks = <&ccu1 CLK_CPU_CORE>;
};
};
clocks {
xtal: xtal {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <12000000>;
};
xtal32: xtal32 {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <32768>;
};
enet_rx_clk: enet_rx_clk {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <0>;
clock-output-names = "enet_rx_clk";
};
enet_tx_clk: enet_tx_clk {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <0>;
clock-output-names = "enet_tx_clk";
};
gp_clkin: gp_clkin {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <0>;
clock-output-names = "gp_clkin";
};
};
soc {
sct_pwm: pwm@40000000 {
compatible = "nxp,lpc1850-sct-pwm";
reg = <0x40000000 0x1000>;
clocks = <&ccu1 CLK_CPU_SCT>;
clock-names = "pwm";
resets = <&rgu 37>;
#pwm-cells = <3>;
status = "disabled";
};
Annotation
- Immediate include surface: `../../armv7-m.dtsi`, `dt-bindings/clock/lpc18xx-cgu.h`, `dt-bindings/clock/lpc18xx-ccu.h`.
- Atlas domain: Architecture Layer / arch/arm.
- Implementation status: atlas-only.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.