arch/arm/boot/dts/nxp/lpc/lpc32xx.dtsi
Source file repositories/reference/linux-study-clean/arch/arm/boot/dts/nxp/lpc/lpc32xx.dtsi
File Facts
- System
- Linux kernel
- Corpus path
arch/arm/boot/dts/nxp/lpc/lpc32xx.dtsi- Extension
.dtsi- Size
- 13641 bytes
- Lines
- 541
- Domain
- Architecture Layer
- Bucket
- arch/arm
- Inferred role
- Architecture Layer: configuration, schema, or hardware description
- Status
- atlas-only
Why This File Exists
CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.
- CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.
Dependency Surface
dt-bindings/clock/lpc32xx-clock.hdt-bindings/interrupt-controller/irq.h
Detected Declarations
- No top-level syscall, struct, function, initcall, or export declaration detected by the generator.
Annotated Snippet
// SPDX-License-Identifier: GPL-2.0+
/*
* NXP LPC32xx SoC
*
* Copyright (C) 2015-2019 Vladimir Zapolskiy <vz@mleia.com>
* Copyright 2012 Roland Stigge <stigge@antcom.de>
*/
#include <dt-bindings/clock/lpc32xx-clock.h>
#include <dt-bindings/interrupt-controller/irq.h>
/ {
#address-cells = <1>;
#size-cells = <1>;
compatible = "nxp,lpc3220";
interrupt-parent = <&mic>;
cpus {
#address-cells = <1>;
#size-cells = <0>;
cpu@0 {
compatible = "arm,arm926ej-s";
device_type = "cpu";
reg = <0x0>;
};
};
clocks {
xtal_32k: xtal_32k {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <32768>;
clock-output-names = "xtal_32k";
};
xtal: xtal {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <13000000>;
clock-output-names = "xtal";
};
};
ahb {
#address-cells = <1>;
#size-cells = <1>;
compatible = "simple-bus";
ranges = <0x00000000 0x00000000 0x10000000>,
<0x20000000 0x20000000 0x30000000>,
<0xe0000000 0xe0000000 0x04000000>;
iram: sram@8000000 {
compatible = "mmio-sram";
reg = <0x08000000 0x20000>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x00000000 0x08000000 0x20000>;
};
/*
* Enable either SLC or MLC
*/
slc: nand-controller@20020000 {
compatible = "nxp,lpc3220-slc";
reg = <0x20020000 0x1000>;
interrupts = <11 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk LPC32XX_CLK_SLC>;
dmas = <&dma 1 1>;
Annotation
- Immediate include surface: `dt-bindings/clock/lpc32xx-clock.h`, `dt-bindings/interrupt-controller/irq.h`.
- Atlas domain: Architecture Layer / arch/arm.
- Implementation status: atlas-only.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.