arch/arm/boot/dts/nxp/lpc/lpc4357.dtsi
Source file repositories/reference/linux-study-clean/arch/arm/boot/dts/nxp/lpc/lpc4357.dtsi
File Facts
- System
- Linux kernel
- Corpus path
arch/arm/boot/dts/nxp/lpc/lpc4357.dtsi- Extension
.dtsi- Size
- 1058 bytes
- Lines
- 53
- Domain
- Architecture Layer
- Bucket
- arch/arm
- Inferred role
- Architecture Layer: configuration, schema, or hardware description
- Status
- atlas-only
Why This File Exists
CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.
- CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.
Dependency Surface
- No C-style include directives detected by the generator.
Detected Declarations
- No top-level syscall, struct, function, initcall, or export declaration detected by the generator.
Annotated Snippet
/ {
compatible = "nxp,lpc4357";
cpus {
cpu@0 {
compatible = "arm,cortex-m4";
};
};
soc {
sram0: sram@10000000 {
compatible = "mmio-sram";
reg = <0x10000000 0x8000>; /* 32 KiB local SRAM */
#address-cells = <1>;
#size-cells = <1>;
ranges;
};
sram1: sram@10080000 {
compatible = "mmio-sram";
reg = <0x10080000 0xa000>; /* 32 + 8 KiB local SRAM */
#address-cells = <1>;
#size-cells = <1>;
ranges;
};
sram2: sram@20000000 {
compatible = "mmio-sram";
reg = <0x20000000 0x10000>; /* 4 x 16 KiB AHB SRAM */
#address-cells = <1>;
#size-cells = <1>;
ranges;
};
};
};
&eeprom {
status = "okay";
};
Annotation
- Atlas domain: Architecture Layer / arch/arm.
- Implementation status: atlas-only.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.