arch/arm/boot/dts/nxp/ls/ls1021a-tsn.dts

Source file repositories/reference/linux-study-clean/arch/arm/boot/dts/nxp/ls/ls1021a-tsn.dts

File Facts

System
Linux kernel
Corpus path
arch/arm/boot/dts/nxp/ls/ls1021a-tsn.dts
Extension
.dts
Size
5033 bytes
Lines
294
Domain
Architecture Layer
Bucket
arch/arm
Inferred role
Architecture Layer: configuration, schema, or hardware description
Status
atlas-only

Why This File Exists

CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.

Dependency Surface

Detected Declarations

Annotated Snippet

// SPDX-License-Identifier: GPL-2.0
/* Copyright 2016-2018 NXP Semiconductors
 * Copyright 2019 Vladimir Oltean <olteanv@gmail.com>
 */

/dts-v1/;
#include "ls1021a.dtsi"

/ {
	model = "NXP LS1021A-TSN Board";
	compatible = "fsl,ls1021a-tsn", "fsl,ls1021a";

	sys_mclk: clock-mclk {
		compatible = "fixed-clock";
		#clock-cells = <0>;
		clock-frequency = <24576000>;
	};

	reg_vdda_codec: regulator-3V3 {
		compatible = "regulator-fixed";
		regulator-name = "3P3V";
		regulator-min-microvolt = <3300000>;
		regulator-max-microvolt = <3300000>;
		regulator-always-on;
	};

	reg_vddio_codec: regulator-2V5 {
		compatible = "regulator-fixed";
		regulator-name = "2P5V";
		regulator-min-microvolt = <2500000>;
		regulator-max-microvolt = <2500000>;
		regulator-always-on;
	};
};

&dspi0 {
	bus-num = <0>;
	status = "okay";

	/* ADG704BRMZ 1:4 SPI mux/demux */
	sja1105: ethernet-switch@1 {
		reg = <0x1>;
		compatible = "nxp,sja1105t";
		/* 12 MHz */
		spi-max-frequency = <12000000>;
		/* Sample data on trailing clock edge */
		spi-cpha;
		/* SPI controller settings for SJA1105 timing requirements */
		fsl,spi-cs-sck-delay = <1000>;
		fsl,spi-sck-cs-delay = <1000>;

		ports {
			#address-cells = <1>;
			#size-cells = <0>;

			port@0 {
				/* ETH5 written on chassis */
				label = "swp5";
				phy-handle = <&rgmii_phy6>;
				phy-mode = "rgmii-id";
				reg = <0>;
			};

			port@1 {
				/* ETH2 written on chassis */
				label = "swp2";
				phy-handle = <&rgmii_phy3>;
				phy-mode = "rgmii-id";
				reg = <1>;
			};

Annotation

Implementation Notes