arch/arm/boot/dts/nxp/vf/vf610-pinfunc.h
Source file repositories/reference/linux-study-clean/arch/arm/boot/dts/nxp/vf/vf610-pinfunc.h
File Facts
- System
- Linux kernel
- Corpus path
arch/arm/boot/dts/nxp/vf/vf610-pinfunc.h- Extension
.h- Size
- 47423 bytes
- Lines
- 857
- Domain
- Architecture Layer
- Bucket
- arch/arm
- Inferred role
- Architecture Layer: implementation source
- Status
- source implementation candidate
Why This File Exists
CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.
- CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.
Dependency Surface
- No C-style include directives detected by the generator.
Detected Declarations
- No top-level syscall, struct, function, initcall, or export declaration detected by the generator.
Annotated Snippet
#ifndef __DTS_VF610_PINFUNC_H
#define __DTS_VF610_PINFUNC_H
/*
* The pin function ID for VF610 is a tuple of:
* <mux_reg input_reg mux_mode input_val>
*/
#define ALT0 0x0
#define ALT1 0x1
#define ALT2 0x2
#define ALT3 0x3
#define ALT4 0x4
#define ALT5 0x5
#define ALT6 0x6
#define ALT7 0x7
#define VF610_PAD_PTA6__GPIO_0 0x000 0x000 ALT0 0x0
#define VF610_PAD_PTA6__RMII_CLKOUT 0x000 0x000 ALT1 0x0
#define VF610_PAD_PTA6__RMII_CLKIN 0x000 0x2F0 ALT2 0x0
#define VF610_PAD_PTA6__DCU1_TCON11 0x000 0x000 ALT4 0x0
#define VF610_PAD_PTA6__DCU1_R2 0x000 0x000 ALT7 0x0
#define VF610_PAD_PTA8__GPIO_1 0x004 0x000 ALT0 0x0
#define VF610_PAD_PTA8__TCLK 0x004 0x000 ALT1 0x0
#define VF610_PAD_PTA8__DCU0_R0 0x004 0x000 ALT4 0x0
#define VF610_PAD_PTA8__MLB_CLK 0x004 0x354 ALT7 0x0
#define VF610_PAD_PTA9__GPIO_2 0x008 0x000 ALT0 0x0
#define VF610_PAD_PTA9__TDI 0x008 0x000 ALT1 0x0
#define VF610_PAD_PTA9__RMII_CLKOUT 0x008 0x000 ALT2 0x0
#define VF610_PAD_PTA9__RMII_CLKIN 0x008 0x2F0 ALT3 0x1
#define VF610_PAD_PTA9__DCU0_R1 0x008 0x000 ALT4 0x0
#define VF610_PAD_PTA9__WDOG_B 0x008 0x000 ALT6 0x0
#define VF610_PAD_PTA10__GPIO_3 0x00C 0x000 ALT0 0x0
#define VF610_PAD_PTA10__TDO 0x00C 0x000 ALT1 0x0
#define VF610_PAD_PTA10__EXT_AUDIO_MCLK 0x00C 0x2EC ALT2 0x0
#define VF610_PAD_PTA10__DCU0_G0 0x00C 0x000 ALT4 0x0
#define VF610_PAD_PTA10__ENET_TS_CLKIN 0x00C 0x2F4 ALT6 0x0
#define VF610_PAD_PTA10__MLB_SIGNAL 0x00C 0x35C ALT7 0x0
#define VF610_PAD_PTA11__GPIO_4 0x010 0x000 ALT0 0x0
#define VF610_PAD_PTA11__TMS 0x010 0x000 ALT1 0x0
#define VF610_PAD_PTA11__DCU0_G1 0x010 0x000 ALT4 0x0
#define VF610_PAD_PTA11__MLB_DATA 0x010 0x358 ALT7 0x0
#define VF610_PAD_PTA12__GPIO_5 0x014 0x000 ALT0 0x0
#define VF610_PAD_PTA12__TRACECK 0x014 0x000 ALT1 0x0
#define VF610_PAD_PTA12__EXT_AUDIO_MCLK 0x014 0x2EC ALT2 0x1
#define VF610_PAD_PTA12__VIU_DATA13 0x014 0x000 ALT6 0x0
#define VF610_PAD_PTA12__I2C0_SCL 0x014 0x33C ALT7 0x0
#define VF610_PAD_PTA16__GPIO_6 0x018 0x000 ALT0 0x0
#define VF610_PAD_PTA16__TRACED0 0x018 0x000 ALT1 0x0
#define VF610_PAD_PTA16__USB0_VBUS_EN 0x018 0x000 ALT2 0x0
#define VF610_PAD_PTA16__ADC1_SE0 0x018 0x000 ALT3 0x0
#define VF610_PAD_PTA16__LCD29 0x018 0x000 ALT4 0x0
#define VF610_PAD_PTA16__SAI2_TX_BCLK 0x018 0x370 ALT5 0x0
#define VF610_PAD_PTA16__VIU_DATA14 0x018 0x000 ALT6 0x0
#define VF610_PAD_PTA16__I2C0_SDA 0x018 0x340 ALT7 0x0
#define VF610_PAD_PTA17__GPIO_7 0x01C 0x000 ALT0 0x0
#define VF610_PAD_PTA17__TRACED1 0x01C 0x000 ALT1 0x0
#define VF610_PAD_PTA17__USB0_VBUS_OC 0x01C 0x000 ALT2 0x0
#define VF610_PAD_PTA17__ADC1_SE1 0x01C 0x000 ALT3 0x0
#define VF610_PAD_PTA17__LCD30 0x01C 0x000 ALT4 0x0
#define VF610_PAD_PTA17__USB0_SOF_PULSE 0x01C 0x000 ALT5 0x0
#define VF610_PAD_PTA17__VIU_DATA15 0x01C 0x000 ALT6 0x0
#define VF610_PAD_PTA17__I2C1_SCL 0x01C 0x344 ALT7 0x0
#define VF610_PAD_PTA18__GPIO_8 0x020 0x000 ALT0 0x0
#define VF610_PAD_PTA18__TRACED2 0x020 0x000 ALT1 0x0
#define VF610_PAD_PTA18__ADC0_SE0 0x020 0x000 ALT2 0x0
#define VF610_PAD_PTA18__FTM1_QD_PHA 0x020 0x334 ALT3 0x0
#define VF610_PAD_PTA18__LCD31 0x020 0x000 ALT4 0x0
#define VF610_PAD_PTA18__SAI2_TX_DATA 0x020 0x000 ALT5 0x0
#define VF610_PAD_PTA18__VIU_DATA16 0x020 0x000 ALT6 0x0
#define VF610_PAD_PTA18__I2C1_SDA 0x020 0x348 ALT7 0x0
#define VF610_PAD_PTA19__GPIO_9 0x024 0x000 ALT0 0x0
#define VF610_PAD_PTA19__TRACED3 0x024 0x000 ALT1 0x0
#define VF610_PAD_PTA19__ADC0_SE1 0x024 0x000 ALT2 0x0
#define VF610_PAD_PTA19__FTM1_QD_PHB 0x024 0x338 ALT3 0x0
#define VF610_PAD_PTA19__LCD32 0x024 0x000 ALT4 0x0
#define VF610_PAD_PTA19__SAI2_TX_SYNC 0x024 0x000 ALT5 0x0
#define VF610_PAD_PTA19__VIU_DATA17 0x024 0x000 ALT6 0x0
#define VF610_PAD_PTA19__QSPI1_A_QSCK 0x024 0x374 ALT7 0x0
#define VF610_PAD_PTA20__GPIO_10 0x028 0x000 ALT0 0x0
#define VF610_PAD_PTA20__TRACED4 0x028 0x000 ALT1 0x0
#define VF610_PAD_PTA20__LCD33 0x028 0x000 ALT4 0x0
#define VF610_PAD_PTA20__UART3_TX 0x028 0x394 ALT6 0x0
#define VF610_PAD_PTA20__DCU1_HSYNC 0x028 0x000 ALT7 0x0
#define VF610_PAD_PTA21__GPIO_11 0x02C 0x000 ALT0 0x0
#define VF610_PAD_PTA21__TRACED5 0x02C 0x000 ALT1 0x0
#define VF610_PAD_PTA21__SAI2_RX_BCLK 0x02C 0x364 ALT5 0x0
#define VF610_PAD_PTA21__UART3_RX 0x02C 0x390 ALT6 0x0
#define VF610_PAD_PTA21__DCU1_VSYNC 0x02C 0x000 ALT7 0x0Annotation
- Atlas domain: Architecture Layer / arch/arm.
- Implementation status: source implementation candidate.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.