arch/arm/boot/dts/qcom/qcom-apq8064.dtsi
Source file repositories/reference/linux-study-clean/arch/arm/boot/dts/qcom/qcom-apq8064.dtsi
File Facts
- System
- Linux kernel
- Corpus path
arch/arm/boot/dts/qcom/qcom-apq8064.dtsi- Extension
.dtsi- Size
- 38421 bytes
- Lines
- 1702
- Domain
- Architecture Layer
- Bucket
- arch/arm
- Inferred role
- Architecture Layer: configuration, schema, or hardware description
- Status
- atlas-only
Why This File Exists
CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.
- CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.
Dependency Surface
dt-bindings/clock/qcom,gcc-msm8960.hdt-bindings/clock/qcom,lcc-msm8960.hdt-bindings/reset/qcom,gcc-msm8960.hdt-bindings/clock/qcom,mmcc-msm8960.hdt-bindings/clock/qcom,rpmcc.hdt-bindings/soc/qcom,gsbi.hdt-bindings/interrupt-controller/irq.hdt-bindings/interrupt-controller/arm-gic.hqcom-apq8064-pins.dtsi
Detected Declarations
- No top-level syscall, struct, function, initcall, or export declaration detected by the generator.
Annotated Snippet
// SPDX-License-Identifier: GPL-2.0
/dts-v1/;
#include <dt-bindings/clock/qcom,gcc-msm8960.h>
#include <dt-bindings/clock/qcom,lcc-msm8960.h>
#include <dt-bindings/reset/qcom,gcc-msm8960.h>
#include <dt-bindings/clock/qcom,mmcc-msm8960.h>
#include <dt-bindings/clock/qcom,rpmcc.h>
#include <dt-bindings/soc/qcom,gsbi.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
/ {
#address-cells = <1>;
#size-cells = <1>;
model = "Qualcomm APQ8064";
compatible = "qcom,apq8064";
interrupt-parent = <&intc>;
reserved-memory {
#address-cells = <1>;
#size-cells = <1>;
ranges;
smem_region: smem@80000000 {
reg = <0x80000000 0x200000>;
no-map;
};
wcnss_mem: wcnss@8f000000 {
reg = <0x8f000000 0x700000>;
no-map;
};
};
cpus {
#address-cells = <1>;
#size-cells = <0>;
cpu0: cpu@0 {
compatible = "qcom,krait";
enable-method = "qcom,kpss-acc-v1";
device_type = "cpu";
reg = <0>;
next-level-cache = <&l2>;
qcom,acc = <&acc0>;
qcom,saw = <&saw0>;
cpu-idle-states = <&cpu_spc>;
};
cpu1: cpu@1 {
compatible = "qcom,krait";
enable-method = "qcom,kpss-acc-v1";
device_type = "cpu";
reg = <1>;
next-level-cache = <&l2>;
qcom,acc = <&acc1>;
qcom,saw = <&saw1>;
cpu-idle-states = <&cpu_spc>;
};
cpu2: cpu@2 {
compatible = "qcom,krait";
enable-method = "qcom,kpss-acc-v1";
device_type = "cpu";
reg = <2>;
next-level-cache = <&l2>;
qcom,acc = <&acc2>;
qcom,saw = <&saw2>;
cpu-idle-states = <&cpu_spc>;
};
Annotation
- Immediate include surface: `dt-bindings/clock/qcom,gcc-msm8960.h`, `dt-bindings/clock/qcom,lcc-msm8960.h`, `dt-bindings/reset/qcom,gcc-msm8960.h`, `dt-bindings/clock/qcom,mmcc-msm8960.h`, `dt-bindings/clock/qcom,rpmcc.h`, `dt-bindings/soc/qcom,gsbi.h`, `dt-bindings/interrupt-controller/irq.h`, `dt-bindings/interrupt-controller/arm-gic.h`.
- Atlas domain: Architecture Layer / arch/arm.
- Implementation status: atlas-only.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.