arch/arm/boot/dts/qcom/qcom-ipq8064.dtsi
Source file repositories/reference/linux-study-clean/arch/arm/boot/dts/qcom/qcom-ipq8064.dtsi
File Facts
- System
- Linux kernel
- Corpus path
arch/arm/boot/dts/qcom/qcom-ipq8064.dtsi- Extension
.dtsi- Size
- 32014 bytes
- Lines
- 1388
- Domain
- Architecture Layer
- Bucket
- arch/arm
- Inferred role
- Architecture Layer: configuration, schema, or hardware description
- Status
- atlas-only
Why This File Exists
CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.
- CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.
Dependency Surface
dt-bindings/interrupt-controller/arm-gic.hdt-bindings/mfd/qcom-rpm.hdt-bindings/clock/qcom,rpmcc.hdt-bindings/clock/qcom,gcc-ipq806x.hdt-bindings/clock/qcom,lcc-ipq806x.hdt-bindings/gpio/gpio.hdt-bindings/reset/qcom,gcc-ipq806x.hdt-bindings/soc/qcom,gsbi.h
Detected Declarations
- No top-level syscall, struct, function, initcall, or export declaration detected by the generator.
Annotated Snippet
// SPDX-License-Identifier: GPL-2.0
/dts-v1/;
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/mfd/qcom-rpm.h>
#include <dt-bindings/clock/qcom,rpmcc.h>
#include <dt-bindings/clock/qcom,gcc-ipq806x.h>
#include <dt-bindings/clock/qcom,lcc-ipq806x.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/reset/qcom,gcc-ipq806x.h>
#include <dt-bindings/soc/qcom,gsbi.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
/ {
#address-cells = <1>;
#size-cells = <1>;
model = "Qualcomm IPQ8064";
compatible = "qcom,ipq8064";
interrupt-parent = <&intc>;
cpus {
#address-cells = <1>;
#size-cells = <0>;
cpu0: cpu@0 {
compatible = "qcom,krait";
enable-method = "qcom,kpss-acc-v1";
device_type = "cpu";
reg = <0>;
next-level-cache = <&l2>;
qcom,acc = <&acc0>;
qcom,saw = <&saw0>;
};
cpu1: cpu@1 {
compatible = "qcom,krait";
enable-method = "qcom,kpss-acc-v1";
device_type = "cpu";
reg = <1>;
next-level-cache = <&l2>;
qcom,acc = <&acc1>;
qcom,saw = <&saw1>;
};
l2: l2-cache {
compatible = "cache";
cache-level = <2>;
cache-unified;
};
};
thermal-zones {
sensor0-thermal {
polling-delay-passive = <0>;
polling-delay = <0>;
thermal-sensors = <&tsens 0>;
trips {
cpu-critical {
temperature = <105000>;
hysteresis = <2000>;
type = "critical";
};
cpu-hot {
temperature = <95000>;
hysteresis = <2000>;
type = "hot";
};
};
Annotation
- Immediate include surface: `dt-bindings/interrupt-controller/arm-gic.h`, `dt-bindings/mfd/qcom-rpm.h`, `dt-bindings/clock/qcom,rpmcc.h`, `dt-bindings/clock/qcom,gcc-ipq806x.h`, `dt-bindings/clock/qcom,lcc-ipq806x.h`, `dt-bindings/gpio/gpio.h`, `dt-bindings/reset/qcom,gcc-ipq806x.h`, `dt-bindings/soc/qcom,gsbi.h`.
- Atlas domain: Architecture Layer / arch/arm.
- Implementation status: atlas-only.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.