arch/arm/boot/dts/qcom/qcom-mdm9615.dtsi

Source file repositories/reference/linux-study-clean/arch/arm/boot/dts/qcom/qcom-mdm9615.dtsi

File Facts

System
Linux kernel
Corpus path
arch/arm/boot/dts/qcom/qcom-mdm9615.dtsi
Extension
.dtsi
Size
8545 bytes
Lines
341
Domain
Architecture Layer
Bucket
arch/arm
Inferred role
Architecture Layer: configuration, schema, or hardware description
Status
atlas-only

Why This File Exists

CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.

Dependency Surface

Detected Declarations

Annotated Snippet

// SPDX-License-Identifier: GPL-2.0+ OR MIT
/*
 * Device Tree Source for Qualcomm MDM9615 SoC
 *
 * Copyright (C) 2016 BayLibre, SAS.
 * Author : Neil Armstrong <narmstrong@baylibre.com>
 */

/dts-v1/;

#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/clock/qcom,gcc-mdm9615.h>
#include <dt-bindings/clock/qcom,lcc-msm8960.h>
#include <dt-bindings/reset/qcom,gcc-mdm9615.h>
#include <dt-bindings/mfd/qcom-rpm.h>
#include <dt-bindings/soc/qcom,gsbi.h>

/ {
	#address-cells = <1>;
	#size-cells = <1>;
	model = "Qualcomm MDM9615";
	compatible = "qcom,mdm9615";
	interrupt-parent = <&intc>;

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		cpu0: cpu@0 {
			compatible = "arm,cortex-a5";
			reg = <0>;
			device_type = "cpu";
			next-level-cache = <&l2>;
		};
	};

	cpu-pmu {
		compatible = "arm,cortex-a5-pmu";
		interrupts = <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_HIGH)>;
	};

	clocks {
		cxo_board: cxo_board {
			compatible = "fixed-clock";
			#clock-cells = <0>;
			clock-frequency = <19200000>;
		};
	};

	vsdcc_fixed: vsdcc-regulator {
		compatible = "regulator-fixed";
		regulator-name = "SDCC Power";
		regulator-min-microvolt = <2700000>;
		regulator-max-microvolt = <2700000>;
		regulator-always-on;
	};

	soc: soc {
		#address-cells = <1>;
		#size-cells = <1>;
		ranges;
		compatible = "simple-bus";

		l2: cache-controller@2040000 {
			compatible = "arm,pl310-cache";
			reg = <0x02040000 0x1000>;
			arm,data-latency = <2 2 0>;
			cache-unified;
			cache-level = <2>;
		};

Annotation

Implementation Notes