arch/arm/boot/dts/renesas/r8a7740.dtsi

Source file repositories/reference/linux-study-clean/arch/arm/boot/dts/renesas/r8a7740.dtsi

File Facts

System
Linux kernel
Corpus path
arch/arm/boot/dts/renesas/r8a7740.dtsi
Extension
.dtsi
Size
24138 bytes
Lines
912
Domain
Architecture Layer
Bucket
arch/arm
Inferred role
Architecture Layer: configuration, schema, or hardware description
Status
atlas-only

Why This File Exists

CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.

Dependency Surface

Detected Declarations

Annotated Snippet

// SPDX-License-Identifier: GPL-2.0
/*
 * Device Tree Source for the R-Mobile A1 (R8A77400) SoC
 *
 * Copyright (C) 2012 Renesas Solutions Corp.
 */

#include <dt-bindings/clock/r8a7740-clock.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/interrupt-controller/irq.h>

/ {
	compatible = "renesas,r8a7740";
	interrupt-parent = <&gic>;
	#address-cells = <1>;
	#size-cells = <1>;

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;
		cpu0: cpu@0 {
			compatible = "arm,cortex-a9";
			device_type = "cpu";
			reg = <0x0>;
			clock-frequency = <800000000>;
			power-domains = <&pd_a3sm>;
			next-level-cache = <&L2>;
		};
	};

	gic: interrupt-controller@c2800000 {
		compatible = "arm,pl390";
		#interrupt-cells = <3>;
		interrupt-controller;
		reg = <0xc2800000 0x1000>,
		      <0xc2000000 0x1000>;
	};

	L2: cache-controller@f0100000 {
		compatible = "arm,pl310-cache";
		reg = <0xf0100000 0x1000>;
		interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
		power-domains = <&pd_a3sm>;
		arm,data-latency = <3 3 3>;
		arm,tag-latency = <2 2 2>;
		arm,shared-override;
		cache-unified;
		cache-level = <2>;
	};

	dbsc3: memory-controller@fe400000 {
		compatible = "renesas,dbsc3-r8a7740";
		reg = <0xfe400000 0x400>;
		power-domains = <&pd_a4s>;
	};

	pmu {
		compatible = "arm,cortex-a9-pmu";
		interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
	};

	replicator {
		compatible = "arm,coresight-static-replicator";
		clocks = <&cpg_clocks R8A7740_CLK_ZTR>;
		clock-names = "atclk";
		power-domains = <&pd_d4>;

		out-ports {
			#address-cells = <1>;
			#size-cells = <0>;

Annotation

Implementation Notes