arch/arm/boot/dts/renesas/r8a77470.dtsi

Source file repositories/reference/linux-study-clean/arch/arm/boot/dts/renesas/r8a77470.dtsi

File Facts

System
Linux kernel
Corpus path
arch/arm/boot/dts/renesas/r8a77470.dtsi
Extension
.dtsi
Size
31525 bytes
Lines
1074
Domain
Architecture Layer
Bucket
arch/arm
Inferred role
Architecture Layer: configuration, schema, or hardware description
Status
atlas-only

Why This File Exists

CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.

Dependency Surface

Detected Declarations

Annotated Snippet

// SPDX-License-Identifier: GPL-2.0
/*
 * Device Tree Source for the r8a77470 SoC
 *
 * Copyright (C) 2018 Renesas Electronics Corp.
 */

#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/clock/r8a77470-cpg-mssr.h>
#include <dt-bindings/power/r8a77470-sysc.h>
/ {
	compatible = "renesas,r8a77470";
	#address-cells = <2>;
	#size-cells = <2>;
	interrupt-parent = <&gic>;

	aliases {
		i2c0 = &i2c0;
		i2c1 = &i2c1;
		i2c2 = &i2c2;
		i2c3 = &i2c3;
		i2c4 = &i2c4;
	};

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		cpu0: cpu@0 {
			device_type = "cpu";
			compatible = "arm,cortex-a7";
			reg = <0>;
			clock-frequency = <1000000000>;
			clocks = <&cpg CPG_CORE R8A77470_CLK_Z2>;
			power-domains = <&sysc R8A77470_PD_CA7_CPU0>;
			enable-method = "renesas,apmu";
			next-level-cache = <&L2_CA7>;
		};

		cpu1: cpu@1 {
			device_type = "cpu";
			compatible = "arm,cortex-a7";
			reg = <1>;
			clock-frequency = <1000000000>;
			clocks = <&cpg CPG_CORE R8A77470_CLK_Z2>;
			power-domains = <&sysc R8A77470_PD_CA7_CPU1>;
			enable-method = "renesas,apmu";
			next-level-cache = <&L2_CA7>;
		};

		L2_CA7: cache-controller-0 {
			compatible = "cache";
			cache-unified;
			cache-level = <2>;
			power-domains = <&sysc R8A77470_PD_CA7_SCU>;
		};
	};

	/* External root clock */
	extal_clk: extal {
		compatible = "fixed-clock";
		#clock-cells = <0>;
		/* This value must be overridden by the board. */
		clock-frequency = <0>;
	};

	pmu {
		compatible = "arm,cortex-a7-pmu";
		interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>,

Annotation

Implementation Notes