arch/arm/boot/dts/renesas/r9a06g032.dtsi

Source file repositories/reference/linux-study-clean/arch/arm/boot/dts/renesas/r9a06g032.dtsi

File Facts

System
Linux kernel
Corpus path
arch/arm/boot/dts/renesas/r9a06g032.dtsi
Extension
.dtsi
Size
22499 bytes
Lines
764
Domain
Architecture Layer
Bucket
arch/arm
Inferred role
Architecture Layer: configuration, schema, or hardware description
Status
atlas-only

Why This File Exists

CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.

Dependency Surface

Detected Declarations

Annotated Snippet

// SPDX-License-Identifier: GPL-2.0
/*
 * Base Device Tree Source for the Renesas RZ/N1D (R9A06G032)
 *
 * Copyright (C) 2018 Renesas Electronics Europe Limited
 *
 */

#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/clock/r9a06g032-sysctrl.h>

/ {
	compatible = "renesas,r9a06g032";
	#address-cells = <1>;
	#size-cells = <1>;
	interrupt-parent = <&gic>;

	/*
	 * The CPUs clock is based on the 'ref' clock (output of OPPDIV divisor)
	 * with x1, x2 or x4 ratio between the CPUs clock frequency and this
	 * 'ref' clock frequency.
	 *
	 * The table below is built on the assumption that the 'ref' clock
	 * frequency is set to 500MHz which is its default value.
	 *
	 * The table should be overridden in the board device-tree file based
	 * on the 'ref' clock frequency if this frequency value is not the
	 * default one.
	 */
	cpu_opp_table: opp-table-cpu {
		compatible = "operating-points-v2";
		opp-shared;

		opp-125000000 {
			opp-hz = /bits/ 64 <125000000>;
			/* ~35 clocks cycles at 125mhz */
			clock-latency-ns = <300>;
		};

		opp-250000000 {
			opp-hz = /bits/ 64 <250000000>;
			clock-latency-ns = <300>;
		};

		opp-500000000 {
			opp-hz = /bits/ 64 <500000000>;
			clock-latency-ns = <300>;
		};
	};

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		cpu@0 {
			device_type = "cpu";
			compatible = "arm,cortex-a7";
			reg = <0>;
			clocks = <&sysctrl R9A06G032_CLK_A7MP>;
			operating-points-v2 = <&cpu_opp_table>;
		};

		cpu@1 {
			device_type = "cpu";
			compatible = "arm,cortex-a7";
			reg = <1>;
			clocks = <&sysctrl R9A06G032_CLK_A7MP>;
			enable-method = "renesas,r9a06g032-smp";
			cpu-release-addr = <0 0x4000c204>;
			operating-points-v2 = <&cpu_opp_table>;

Annotation

Implementation Notes