arch/arm/boot/dts/renesas/sh73a0.dtsi

Source file repositories/reference/linux-study-clean/arch/arm/boot/dts/renesas/sh73a0.dtsi

File Facts

System
Linux kernel
Corpus path
arch/arm/boot/dts/renesas/sh73a0.dtsi
Extension
.dtsi
Size
27226 bytes
Lines
949
Domain
Architecture Layer
Bucket
arch/arm
Inferred role
Architecture Layer: configuration, schema, or hardware description
Status
atlas-only

Why This File Exists

CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.

Dependency Surface

Detected Declarations

Annotated Snippet

// SPDX-License-Identifier: GPL-2.0
/*
 * Device Tree Source for the SH-Mobile AG5 (R8A73A00/SH73A0) SoC
 *
 * Copyright (C) 2012 Renesas Solutions Corp.
 */

#include <dt-bindings/clock/sh73a0-clock.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/interrupt-controller/irq.h>

/ {
	compatible = "renesas,sh73a0";
	interrupt-parent = <&gic>;
	#address-cells = <1>;
	#size-cells = <1>;

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		cpu0: cpu@0 {
			device_type = "cpu";
			compatible = "arm,cortex-a9";
			reg = <0>;
			clock-frequency = <1196000000>;
			clocks = <&cpg_clocks SH73A0_CLK_Z>;
			power-domains = <&pd_a2sl>;
			next-level-cache = <&L2>;
		};
		cpu1: cpu@1 {
			device_type = "cpu";
			compatible = "arm,cortex-a9";
			reg = <1>;
			clock-frequency = <1196000000>;
			clocks = <&cpg_clocks SH73A0_CLK_Z>;
			power-domains = <&pd_a2sl>;
			next-level-cache = <&L2>;
		};
	};

	timer@f0000200 {
		compatible = "arm,cortex-a9-global-timer";
		reg = <0xf0000200 0x100>;
		interrupts = <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_EDGE_RISING)>;
		clocks = <&periph_clk>;
	};

	timer@f0000600 {
		compatible = "arm,cortex-a9-twd-timer";
		reg = <0xf0000600 0x20>;
		interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_EDGE_RISING)>;
		clocks = <&periph_clk>;
	};

	gic: interrupt-controller@f0001000 {
		compatible = "arm,cortex-a9-gic";
		#interrupt-cells = <3>;
		interrupt-controller;
		reg = <0xf0001000 0x1000>,
		      <0xf0000100 0x100>;
	};

	L2: cache-controller@f0100000 {
		compatible = "arm,pl310-cache";
		reg = <0xf0100000 0x1000>;
		interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
		power-domains = <&pd_a3sm>;
		arm,data-latency = <3 3 3>;
		arm,tag-latency = <2 2 2>;

Annotation

Implementation Notes