arch/arm/boot/dts/rockchip/rv1126-edgeble-neu2.dtsi
Source file repositories/reference/linux-study-clean/arch/arm/boot/dts/rockchip/rv1126-edgeble-neu2.dtsi
File Facts
- System
- Linux kernel
- Corpus path
arch/arm/boot/dts/rockchip/rv1126-edgeble-neu2.dtsi- Extension
.dtsi- Size
- 7798 bytes
- Lines
- 346
- Domain
- Architecture Layer
- Bucket
- arch/arm
- Inferred role
- Architecture Layer: configuration, schema, or hardware description
- Status
- atlas-only
Why This File Exists
CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.
- CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.
Dependency Surface
- No C-style include directives detected by the generator.
Detected Declarations
- No top-level syscall, struct, function, initcall, or export declaration detected by the generator.
Annotated Snippet
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright (c) 2020 Rockchip Electronics Co., Ltd.
* Copyright (c) 2022 Edgeble AI Technologies Pvt. Ltd.
*/
/ {
compatible = "edgeble,neural-compute-module-2", "rockchip,rv1126";
aliases {
mmc0 = &emmc;
};
vccio_flash: regulator-vccio-flash {
compatible = "regulator-fixed";
enable-active-high;
gpio = <&gpio0 RK_PB3 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&flash_vol_sel>;
regulator-name = "vccio_flash";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
vin-supply = <&vcc_3v3>;
};
sdio_pwrseq: pwrseq-sdio {
compatible = "mmc-pwrseq-simple";
clocks = <&rk809 1>;
clock-names = "ext_clock";
pinctrl-names = "default";
pinctrl-0 = <&wifi_enable_h>;
reset-gpios = <&gpio1 RK_PD0 GPIO_ACTIVE_LOW>;
};
};
&cpu0 {
cpu-supply = <&vdd_arm>;
};
&emmc {
bus-width = <8>;
non-removable;
pinctrl-names = "default";
pinctrl-0 = <&emmc_bus8 &emmc_cmd &emmc_clk>;
rockchip,default-sample-phase = <90>;
vmmc-supply = <&vcc_3v3>;
vqmmc-supply = <&vccio_flash>;
status = "okay";
};
&i2c0 {
clock-frequency = <400000>;
status = "okay";
rk809: pmic@20 {
compatible = "rockchip,rk809";
reg = <0x20>;
interrupt-parent = <&gpio0>;
interrupts = <RK_PB1 IRQ_TYPE_LEVEL_LOW>;
#clock-cells = <1>;
clock-output-names = "rk808-clkout1", "rk808-clkout2";
pinctrl-names = "default";
pinctrl-0 = <&pmic_int_l>;
rockchip,system-power-controller;
wakeup-source;
vcc1-supply = <&vcc5v0_sys>;
vcc2-supply = <&vcc5v0_sys>;
Annotation
- Atlas domain: Architecture Layer / arch/arm.
- Implementation status: atlas-only.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.