arch/arm/boot/dts/rockchip/rv1126-edgeble-neu2-io.dts

Source file repositories/reference/linux-study-clean/arch/arm/boot/dts/rockchip/rv1126-edgeble-neu2-io.dts

File Facts

System
Linux kernel
Corpus path
arch/arm/boot/dts/rockchip/rv1126-edgeble-neu2-io.dts
Extension
.dts
Size
2501 bytes
Lines
112
Domain
Architecture Layer
Bucket
arch/arm
Inferred role
Architecture Layer: configuration, schema, or hardware description
Status
atlas-only

Why This File Exists

CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.

Dependency Surface

Detected Declarations

Annotated Snippet

// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
 * Copyright (c) 2020 Rockchip Electronics Co., Ltd.
 * Copyright (c) 2022 Edgeble AI Technologies Pvt. Ltd.
 */

/dts-v1/;
#include "rv1126.dtsi"
#include "rv1126-edgeble-neu2.dtsi"

/ {
	model = "Edgeble Neu2 IO Board";
	compatible = "edgeble,neural-compute-module-2-io",
		     "edgeble,neural-compute-module-2", "rockchip,rv1126";

	aliases {
		serial2 = &uart2;
	};

	chosen {
		stdout-path = "serial2:1500000n8";
	};

	vcc12v_dcin: regulator-vcc12v-dcin {
		compatible = "regulator-fixed";
		regulator-name = "vcc12v_dcin";
		regulator-always-on;
		regulator-boot-on;
		regulator-min-microvolt = <12000000>;
		regulator-max-microvolt = <12000000>;
	};

	vcc5v0_sys: regulator-vcc5v0-sys {
		compatible = "regulator-fixed";
		regulator-name = "vcc5v0_sys";
		regulator-always-on;
		regulator-boot-on;
		regulator-min-microvolt = <5000000>;
		regulator-max-microvolt = <5000000>;
		vin-supply = <&vcc12v_dcin>;
	};

	v3v3_sys: regulator-v3v3-sys {
		compatible = "regulator-fixed";
		regulator-name = "v3v3_sys";
		regulator-always-on;
		regulator-boot-on;
		regulator-min-microvolt = <3300000>;
		regulator-max-microvolt = <3300000>;
		vin-supply = <&vcc5v0_sys>;
	};
};

&gmac {
	assigned-clocks = <&cru CLK_GMAC_SRC>, <&cru CLK_GMAC_TX_RX>,
			  <&cru CLK_GMAC_ETHERNET_OUT>;
	assigned-clock-parents = <&cru CLK_GMAC_SRC_M1>, <&cru RGMII_MODE_CLK>;
	assigned-clock-rates = <125000000>, <0>, <25000000>;
	clock_in_out = "input";
	phy-handle = <&phy>;
	phy-mode = "rgmii";
	phy-supply = <&vcc_3v3>;
	pinctrl-names = "default";
	pinctrl-0 = <&rgmiim1_miim &rgmiim1_bus2 &rgmiim1_bus4 &clk_out_ethernetm1_pins>;
	tx_delay = <0x2a>;
	rx_delay = <0x1a>;
	status = "okay";
};

&mdio {

Annotation

Implementation Notes