arch/arm/boot/dts/samsung/exynos-mfc-reserved-memory.dtsi
Source file repositories/reference/linux-study-clean/arch/arm/boot/dts/samsung/exynos-mfc-reserved-memory.dtsi
File Facts
- System
- Linux kernel
- Corpus path
arch/arm/boot/dts/samsung/exynos-mfc-reserved-memory.dtsi- Extension
.dtsi- Size
- 580 bytes
- Lines
- 33
- Domain
- Architecture Layer
- Bucket
- arch/arm
- Inferred role
- Architecture Layer: configuration, schema, or hardware description
- Status
- atlas-only
Why This File Exists
CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.
- CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.
Dependency Surface
- No C-style include directives detected by the generator.
Detected Declarations
- No top-level syscall, struct, function, initcall, or export declaration detected by the generator.
Annotated Snippet
// SPDX-License-Identifier: GPL-2.0
/*
* Samsung's Exynos SoC MFC (Video Codec) reserved memory common definition.
*
* Copyright (c) 2016 Samsung Electronics Co., Ltd
*/
/ {
reserved-memory {
#address-cells = <1>;
#size-cells = <1>;
ranges;
mfc_left: region-mfc-left {
compatible = "shared-dma-pool";
no-map;
size = <0x2400000>;
alignment = <0x100000>;
};
mfc_right: region-mfc-right {
compatible = "shared-dma-pool";
no-map;
size = <0x800000>;
alignment = <0x100000>;
};
};
};
&mfc {
memory-region = <&mfc_left>, <&mfc_right>;
};
Annotation
- Atlas domain: Architecture Layer / arch/arm.
- Implementation status: atlas-only.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.