arch/arm/boot/dts/samsung/exynos4212-tab3-wifi8.dts
Source file repositories/reference/linux-study-clean/arch/arm/boot/dts/samsung/exynos4212-tab3-wifi8.dts
File Facts
- System
- Linux kernel
- Corpus path
arch/arm/boot/dts/samsung/exynos4212-tab3-wifi8.dts- Extension
.dts- Size
- 554 bytes
- Lines
- 27
- Domain
- Architecture Layer
- Bucket
- arch/arm
- Inferred role
- Architecture Layer: configuration, schema, or hardware description
- Status
- atlas-only
Why This File Exists
CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.
- CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.
Dependency Surface
exynos4212-tab3.dtsi
Detected Declarations
- No top-level syscall, struct, function, initcall, or export declaration detected by the generator.
Annotated Snippet
// SPDX-License-Identifier: GPL-2.0
/*
* Samsung's Exynos4212 based Galaxy Tab 3 8.0 WiFi board device tree
* source
*
* Copyright (c) 2013 Samsung Electronics Co., Ltd.
* http://www.samsung.com
*/
/dts-v1/;
#include "exynos4212-tab3.dtsi"
/ {
model = "Samsung Galaxy Tab 3 8.0 WiFi (SM-T310) based on Exynos4212";
compatible = "samsung,t310", "samsung,tab3", "samsung,exynos4212", "samsung,exynos4";
chassis-type = "tablet";
};
&i2c_lightsensor {
status = "okay";
lightsensor@10 {
compatible = "capella,cm3323";
reg = <0x10>;
};
};
Annotation
- Immediate include surface: `exynos4212-tab3.dtsi`.
- Atlas domain: Architecture Layer / arch/arm.
- Implementation status: atlas-only.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.