arch/arm/boot/dts/samsung/exynos5422-odroidxu3-common.dtsi
Source file repositories/reference/linux-study-clean/arch/arm/boot/dts/samsung/exynos5422-odroidxu3-common.dtsi
File Facts
- System
- Linux kernel
- Corpus path
arch/arm/boot/dts/samsung/exynos5422-odroidxu3-common.dtsi- Extension
.dtsi- Size
- 11238 bytes
- Lines
- 505
- Domain
- Architecture Layer
- Bucket
- arch/arm
- Inferred role
- Architecture Layer: configuration, schema, or hardware description
- Status
- atlas-only
Why This File Exists
CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.
- CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.
Dependency Surface
dt-bindings/input/input.hexynos5422-odroid-core.dtsi
Detected Declarations
- No top-level syscall, struct, function, initcall, or export declaration detected by the generator.
Annotated Snippet
// SPDX-License-Identifier: GPL-2.0
/*
* Hardkernel Odroid XU3/XU3-Lite/XU4 boards common device tree source
*
* Copyright (c) 2013 Samsung Electronics Co., Ltd.
* http://www.samsung.com
* Copyright (c) 2014 Collabora Ltd.
* Copyright (c) 2015 Lukasz Majewski <l.majewski@samsung.com>
* Anand Moon <linux.amoon@gmail.com>
*/
#include <dt-bindings/input/input.h>
#include "exynos5422-odroid-core.dtsi"
/ {
aliases {
mmc0 = &mmc_0;
};
gpio-keys {
compatible = "gpio-keys";
pinctrl-names = "default";
pinctrl-0 = <&power_key>;
power-key {
/*
* The power button (SW2) is connected to the PWRON
* pin (active high) of the S2MPS11 PMIC, which acts
* as a 16ms debouce filter and signal inverter with
* output on ONOB pin (active low). ONOB PMIC pin is
* then connected to XEINT3 SoC pin.
*/
gpios = <&gpx0 3 GPIO_ACTIVE_LOW>;
linux,code = <KEY_POWER>;
label = "power key";
debounce-interval = <0>;
wakeup-source;
};
};
emmc_pwrseq: pwrseq {
pinctrl-0 = <&emmc_nrst_pin>;
pinctrl-names = "default";
compatible = "mmc-pwrseq-emmc";
reset-gpios = <&gpd1 0 GPIO_ACTIVE_LOW>;
};
fan0: pwm-fan {
compatible = "pwm-fan";
pwms = <&pwm 0 20972 0>;
#cooling-cells = <2>;
cooling-levels = <0 130 170 230>;
};
thermal-zones {
cpu0_thermal: cpu0-thermal {
thermal-sensors = <&tmu_cpu0>;
polling-delay-passive = <0>;
polling-delay = <0>;
trips {
cpu0_alert0: cpu-alert-0 {
temperature = <50000>; /* millicelsius */
hysteresis = <5000>; /* millicelsius */
type = "active";
};
cpu0_alert1: cpu-alert-1 {
temperature = <60000>; /* millicelsius */
hysteresis = <5000>; /* millicelsius */
type = "active";
};
Annotation
- Immediate include surface: `dt-bindings/input/input.h`, `exynos5422-odroid-core.dtsi`.
- Atlas domain: Architecture Layer / arch/arm.
- Implementation status: atlas-only.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.