arch/arm/boot/dts/samsung/exynos54xx.dtsi

Source file repositories/reference/linux-study-clean/arch/arm/boot/dts/samsung/exynos54xx.dtsi

File Facts

System
Linux kernel
Corpus path
arch/arm/boot/dts/samsung/exynos54xx.dtsi
Extension
.dtsi
Size
5436 bytes
Lines
211
Domain
Architecture Layer
Bucket
arch/arm
Inferred role
Architecture Layer: configuration, schema, or hardware description
Status
atlas-only

Why This File Exists

CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.

Dependency Surface

Detected Declarations

Annotated Snippet

// SPDX-License-Identifier: GPL-2.0
/*
 * Samsung's Exynos54xx SoC series common device tree source
 *
 * Copyright (c) 2012-2013 Samsung Electronics Co., Ltd.
 *		http://www.samsung.com
 * Copyright (c) 2016 Krzysztof Kozlowski
 *
 * Device nodes common for Samsung Exynos5410/5420/5422/5800. Specific
 * Exynos 54xx SoCs should include this file and customize it further
 * (e.g. with clocks).
 */

#include "exynos5.dtsi"

/ {
	compatible = "samsung,exynos5";

	aliases {
		i2c4 = &hsi2c_4;
		i2c5 = &hsi2c_5;
		i2c6 = &hsi2c_6;
		i2c7 = &hsi2c_7;
		usbdrdphy0 = &usbdrd_phy0;
		usbdrdphy1 = &usbdrd_phy1;
	};

	arm_a7_pmu: arm-a7-pmu {
		compatible = "arm,cortex-a7-pmu";
		interrupt-parent = <&gic>;
		interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>;
		status = "disabled";
	};

	arm_a15_pmu: arm-a15-pmu {
		compatible = "arm,cortex-a15-pmu";
		interrupt-parent = <&combiner>;
		interrupts = <1 2>,
			     <7 0>,
			     <16 6>,
			     <19 2>;
		status = "disabled";
	};

	timer: timer {
		compatible = "arm,armv7-timer";
		interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
			     <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
			     <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
			     <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
		clock-frequency = <24000000>;
	};

	soc: soc {
		sram@2020000 {
			compatible = "mmio-sram";
			reg = <0x02020000 0x54000>;
			#address-cells = <1>;
			#size-cells = <1>;
			ranges = <0 0x02020000 0x54000>;

			smp-sram@0 {
				compatible = "samsung,exynos4210-sysram";
				reg = <0x0 0x1000>;
			};

			smp-sram@53000 {

Annotation

Implementation Notes