arch/arm/boot/dts/sigmastar/mstar-v7.dtsi
Source file repositories/reference/linux-study-clean/arch/arm/boot/dts/sigmastar/mstar-v7.dtsi
File Facts
- System
- Linux kernel
- Corpus path
arch/arm/boot/dts/sigmastar/mstar-v7.dtsi- Extension
.dtsi- Size
- 4327 bytes
- Lines
- 193
- Domain
- Architecture Layer
- Bucket
- arch/arm
- Inferred role
- Architecture Layer: configuration, schema, or hardware description
- Status
- atlas-only
Why This File Exists
CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.
- CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.
Dependency Surface
dt-bindings/interrupt-controller/irq.hdt-bindings/interrupt-controller/arm-gic.hdt-bindings/clock/mstar-msc313-mpll.h
Detected Declarations
- No top-level syscall, struct, function, initcall, or export declaration detected by the generator.
Annotated Snippet
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* Copyright (c) 2020 thingy.jp.
* Author: Daniel Palmer <daniel@thingy.jp>
*/
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/clock/mstar-msc313-mpll.h>
/ {
#address-cells = <1>;
#size-cells = <1>;
interrupt-parent = <&gic>;
cpus: cpus {
#address-cells = <1>;
#size-cells = <0>;
cpu0: cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-a7";
reg = <0x0>;
clocks = <&cpupll>;
clock-names = "cpuclk";
};
};
arch_timer {
compatible = "arm,armv7-timer";
interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2)
| IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2)
| IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2)
| IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2)
| IRQ_TYPE_LEVEL_LOW)>;
/*
* we shouldn't need this but the vendor
* u-boot is broken
*/
clock-frequency = <6000000>;
arm,cpu-registers-not-fw-configured;
};
pmu: pmu {
compatible = "arm,cortex-a7-pmu";
interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
interrupt-affinity = <&cpu0>;
};
clocks: clocks {
xtal: xtal {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <24000000>;
};
rtc_xtal: rtc_xtal {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <32768>;
status = "disabled";
};
xtal_div2: xtal_div2 {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
clocks = <&xtal>;
Annotation
- Immediate include surface: `dt-bindings/interrupt-controller/irq.h`, `dt-bindings/interrupt-controller/arm-gic.h`, `dt-bindings/clock/mstar-msc313-mpll.h`.
- Atlas domain: Architecture Layer / arch/arm.
- Implementation status: atlas-only.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.