arch/arm/boot/dts/socionext/uniphier-pro5.dtsi
Source file repositories/reference/linux-study-clean/arch/arm/boot/dts/socionext/uniphier-pro5.dtsi
File Facts
- System
- Linux kernel
- Corpus path
arch/arm/boot/dts/socionext/uniphier-pro5.dtsi- Extension
.dtsi- Size
- 18119 bytes
- Lines
- 708
- Domain
- Architecture Layer
- Bucket
- arch/arm
- Inferred role
- Architecture Layer: configuration, schema, or hardware description
- Status
- atlas-only
Why This File Exists
CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.
- CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.
Dependency Surface
dt-bindings/interrupt-controller/arm-gic.huniphier-pinctrl.dtsi
Detected Declarations
- No top-level syscall, struct, function, initcall, or export declaration detected by the generator.
Annotated Snippet
// SPDX-License-Identifier: GPL-2.0+ OR MIT
//
// Device Tree Source for UniPhier Pro5 SoC
//
// Copyright (C) 2015-2016 Socionext Inc.
// Author: Masahiro Yamada <yamada.masahiro@socionext.com>
#include <dt-bindings/interrupt-controller/arm-gic.h>
/ {
compatible = "socionext,uniphier-pro5";
#address-cells = <1>;
#size-cells = <1>;
cpus {
#address-cells = <1>;
#size-cells = <0>;
cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-a9";
reg = <0>;
clocks = <&sys_clk 32>;
enable-method = "psci";
next-level-cache = <&l2>;
operating-points-v2 = <&cpu_opp>;
};
cpu@1 {
device_type = "cpu";
compatible = "arm,cortex-a9";
reg = <1>;
clocks = <&sys_clk 32>;
enable-method = "psci";
next-level-cache = <&l2>;
operating-points-v2 = <&cpu_opp>;
};
};
cpu_opp: opp-table {
compatible = "operating-points-v2";
opp-shared;
opp-100000000 {
opp-hz = /bits/ 64 <100000000>;
clock-latency-ns = <300>;
};
opp-116667000 {
opp-hz = /bits/ 64 <116667000>;
clock-latency-ns = <300>;
};
opp-150000000 {
opp-hz = /bits/ 64 <150000000>;
clock-latency-ns = <300>;
};
opp-175000000 {
opp-hz = /bits/ 64 <175000000>;
clock-latency-ns = <300>;
};
opp-200000000 {
opp-hz = /bits/ 64 <200000000>;
clock-latency-ns = <300>;
};
opp-233334000 {
opp-hz = /bits/ 64 <233334000>;
clock-latency-ns = <300>;
};
opp-300000000 {
opp-hz = /bits/ 64 <300000000>;
clock-latency-ns = <300>;
Annotation
- Immediate include surface: `dt-bindings/interrupt-controller/arm-gic.h`, `uniphier-pinctrl.dtsi`.
- Atlas domain: Architecture Layer / arch/arm.
- Implementation status: atlas-only.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.