arch/arm/boot/dts/socionext/uniphier-support-card.dtsi

File Facts

System

Linux kernel

Corpus path

arch/arm/boot/dts/socionext/uniphier-support-card.dtsi

Extension

.dtsi

Size

659 bytes

Lines

28

Domain

Architecture Layer

Bucket

arch/arm

Inferred role

Architecture Layer: configuration, schema, or hardware description

Status

atlas-only

Why This File Exists

CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.

• CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.

Dependency Surface

• No C-style include directives detected by the generator.

Detected Declarations

• No top-level syscall, struct, function, initcall, or export declaration detected by the generator.

Annotated Snippet

// SPDX-License-Identifier: GPL-2.0+ OR MIT
//
// Device Tree Source for UniPhier Support Card (Expansion Board)
//
// Copyright (C) 2015-2017 Socionext Inc.
//   Author: Masahiro Yamada <yamada.masahiro@socionext.com>

&system_bus {
	status = "okay";
	ranges = <1 0x00000000 0x42000000 0x02000000>;

	ethsc: ethernet@1,1f00000 {
		compatible = "smsc,lan9118", "smsc,lan9115";
		reg = <1 0x01f00000 0x1000>;
		phy-mode = "mii";
		reg-io-width = <4>;
		interrupt-parent = <&gpio>;
	};

	serialsc: serial@1,1fb0000 {
		compatible = "ns16550a";
		reg = <1 0x01fb0000 0x20>;
		clock-frequency = <12288000>;
		reg-shift = <1>;
		interrupt-parent = <&gpio>;
	};
};

Annotation

• Atlas domain: Architecture Layer / arch/arm.
• Implementation status: atlas-only.

Implementation Notes

• This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
• Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
• Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.