arch/arm/boot/dts/st/spear1340.dtsi
Source file repositories/reference/linux-study-clean/arch/arm/boot/dts/st/spear1340.dtsi
File Facts
- System
- Linux kernel
- Corpus path
arch/arm/boot/dts/st/spear1340.dtsi- Extension
.dtsi- Size
- 3785 bytes
- Lines
- 168
- Domain
- Architecture Layer
- Bucket
- arch/arm
- Inferred role
- Architecture Layer: configuration, schema, or hardware description
- Status
- atlas-only
Why This File Exists
CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.
- CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.
Dependency Surface
- No C-style include directives detected by the generator.
Detected Declarations
- No top-level syscall, struct, function, initcall, or export declaration detected by the generator.
Annotated Snippet
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* DTS file for all SPEAr1340 SoCs
*
* Copyright 2012 Viresh Kumar <vireshk@kernel.org>
*/
/include/ "spear13xx.dtsi"
/ {
compatible = "st,spear1340";
ahb {
spics: spics@e0700000 {
compatible = "st,spear-spics-gpio";
reg = <0xe0700000 0x1000>;
st-spics,peripcfg-reg = <0x42c>;
st-spics,sw-enable-bit = <21>;
st-spics,cs-value-bit = <20>;
st-spics,cs-enable-mask = <3>;
st-spics,cs-enable-shift = <18>;
gpio-controller;
#gpio-cells = <2>;
status = "disabled";
};
miphy0: miphy@eb800000 {
compatible = "st,spear1340-miphy";
reg = <0xeb800000 0x4000>;
misc = <&misc>;
#phy-cells = <1>;
status = "disabled";
};
ahci0: ahci@b1000000 {
compatible = "snps,spear-ahci";
reg = <0xb1000000 0x10000>;
interrupts = <0 72 0x4>;
phys = <&miphy0 0>;
phy-names = "sata-phy";
status = "disabled";
};
pcie0: pcie@b1000000 {
compatible = "st,spear1340-pcie", "snps,dw-pcie";
reg = <0xb1000000 0x4000>, <0x80000000 0x20000>;
reg-names = "dbi", "config";
interrupts = <0 68 0x4>;
num-lanes = <1>;
phys = <&miphy0 1>;
phy-names = "pcie-phy";
#address-cells = <3>;
#size-cells = <2>;
device_type = "pci";
ranges = <0x81000000 0 0 0x80020000 0 0x00010000 /* downstream I/O */
0x82000000 0 0x80030000 0xc0030000 0 0x0ffd0000>; /* non-prefetchable memory */
bus-range = <0x00 0xff>;
status = "disabled";
};
i2s-play@b2400000 {
compatible = "snps,designware-i2s";
reg = <0xb2400000 0x10000>;
interrupt-names = "play_irq";
interrupts = <0 98 0x4>,
<0 99 0x4>;
play;
channel = <8>;
status = "disabled";
Annotation
- Atlas domain: Architecture Layer / arch/arm.
- Implementation status: atlas-only.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.