arch/arm/boot/dts/st/ste-dbx5x0.dtsi

Source file repositories/reference/linux-study-clean/arch/arm/boot/dts/st/ste-dbx5x0.dtsi

File Facts

System
Linux kernel
Corpus path
arch/arm/boot/dts/st/ste-dbx5x0.dtsi
Extension
.dtsi
Size
32375 bytes
Lines
1239
Domain
Architecture Layer
Bucket
arch/arm
Inferred role
Architecture Layer: configuration, schema, or hardware description
Status
atlas-only

Why This File Exists

CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.

Dependency Surface

Detected Declarations

Annotated Snippet

// SPDX-License-Identifier: GPL-2.0-or-later
/*
 * Copyright 2012 Linaro Ltd
 */

#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/clock/ste-db8500-clkout.h>
#include <dt-bindings/reset/stericsson,db8500-prcc-reset.h>
#include <dt-bindings/mfd/dbx500-prcmu.h>
#include <dt-bindings/arm/ux500_pm_domains.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/thermal/thermal.h>

/ {
	#address-cells = <1>;
	#size-cells = <1>;

	/* This stablilizes the device enumeration */
	aliases {
		i2c0 = &i2c0;
		i2c1 = &i2c1;
		i2c2 = &i2c2;
		i2c3 = &i2c3;
		i2c4 = &i2c4;
		spi0 = &spi0;
		spi1 = &spi1;
		spi2 = &spi2;
		spi3 = &spi3;
		serial0 = &serial0;
		serial1 = &serial1;
		serial2 = &serial2;
	};

	chosen {
	};

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;
		enable-method = "ste,dbx500-smp";

		cpu-map {
			cluster0 {
				core0 {
					cpu = <&CPU0>;
				};
				core1 {
					cpu = <&CPU1>;
				};
			};
		};
		CPU0: cpu@300 {
			device_type = "cpu";
			compatible = "arm,cortex-a9";
			reg = <0x300>;
			clocks = <&prcmu_clk PRCMU_ARMSS>;
			clock-names = "cpu";
			clock-latency = <20000>;
			#cooling-cells = <2>;
		};
		CPU1: cpu@301 {
			device_type = "cpu";
			compatible = "arm,cortex-a9";
			reg = <0x301>;
		};
	};

	thermal-zones {
		/*

Annotation

Implementation Notes