arch/arm/boot/dts/st/ste-dbx5x0-pinctrl.dtsi
Source file repositories/reference/linux-study-clean/arch/arm/boot/dts/st/ste-dbx5x0-pinctrl.dtsi
File Facts
- System
- Linux kernel
- Corpus path
arch/arm/boot/dts/st/ste-dbx5x0-pinctrl.dtsi- Extension
.dtsi- Size
- 14988 bytes
- Lines
- 700
- Domain
- Architecture Layer
- Bucket
- arch/arm
- Inferred role
- Architecture Layer: configuration, schema, or hardware description
- Status
- atlas-only
Why This File Exists
CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.
- CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.
Dependency Surface
ste-nomadik-pinctrl.dtsi
Detected Declarations
- No top-level syscall, struct, function, initcall, or export declaration detected by the generator.
Annotated Snippet
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* Copyright 2013 Linaro Ltd.
*/
#include "ste-nomadik-pinctrl.dtsi"
&pinctrl {
/* Settings for all UART default and sleep states */
uart0 {
u0_a_1_default: u0_a_1_default {
default_mux {
function = "u0";
groups = "u0_a_1";
};
default_cfg1 {
pins = "GPIO0_AJ5", "GPIO2_AH4"; /* CTS+RXD */
ste,config = <&in_pu>;
};
default_cfg2 {
pins = "GPIO1_AJ3", "GPIO3_AH3"; /* RTS+TXD */
ste,config = <&out_hi>;
};
};
u0_a_1_sleep: u0_a_1_sleep {
sleep_cfg1 {
pins = "GPIO0_AJ5", "GPIO2_AH4"; /* CTS+RXD */
ste,config = <&slpm_in_wkup_pdis>;
};
sleep_cfg2 {
pins = "GPIO1_AJ3"; /* RTS */
ste,config = <&slpm_out_hi_wkup_pdis>;
};
sleep_cfg3 {
pins = "GPIO3_AH3"; /* TXD */
ste,config = <&slpm_out_wkup_pdis>;
};
};
};
uart1 {
u1rxtx_a_1_default: u1rxtx_a_1_default {
default_mux {
function = "u1";
groups = "u1rxtx_a_1";
};
default_cfg1 {
pins = "GPIO4_AH6"; /* RXD */
ste,config = <&in_pu>;
};
default_cfg2 {
pins = "GPIO5_AG6"; /* TXD */
ste,config = <&out_hi>;
};
};
u1rxtx_a_1_sleep: u1rxtx_a_1_sleep {
sleep_cfg1 {
pins = "GPIO4_AH6"; /* RXD */
ste,config = <&slpm_in_wkup_pdis>;
};
sleep_cfg2 {
pins = "GPIO5_AG6"; /* TXD */
ste,config = <&slpm_out_wkup_pdis>;
};
};
u1ctsrts_a_1_default: u1ctsrts_a_1_default {
default_mux {
Annotation
- Immediate include surface: `ste-nomadik-pinctrl.dtsi`.
- Atlas domain: Architecture Layer / arch/arm.
- Implementation status: atlas-only.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.