arch/arm/boot/dts/st/stih407-family.dtsi
Source file repositories/reference/linux-study-clean/arch/arm/boot/dts/st/stih407-family.dtsi
File Facts
- System
- Linux kernel
- Corpus path
arch/arm/boot/dts/st/stih407-family.dtsi- Extension
.dtsi- Size
- 25068 bytes
- Lines
- 993
- Domain
- Architecture Layer
- Bucket
- arch/arm
- Inferred role
- Architecture Layer: configuration, schema, or hardware description
- Status
- atlas-only
Why This File Exists
CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.
- CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.
Dependency Surface
stih407-pinctrl.dtsidt-bindings/mfd/st-lpc.hdt-bindings/phy/phy.hdt-bindings/reset/stih407-resets.hdt-bindings/interrupt-controller/irq-st.h
Detected Declarations
- No top-level syscall, struct, function, initcall, or export declaration detected by the generator.
Annotated Snippet
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (C) 2014 STMicroelectronics Limited.
* Author: Giuseppe Cavallaro <peppe.cavallaro@st.com>
*/
#include "stih407-pinctrl.dtsi"
#include <dt-bindings/mfd/st-lpc.h>
#include <dt-bindings/phy/phy.h>
#include <dt-bindings/reset/stih407-resets.h>
#include <dt-bindings/interrupt-controller/irq-st.h>
/ {
#address-cells = <1>;
#size-cells = <1>;
reserved-memory {
#address-cells = <1>;
#size-cells = <1>;
ranges;
gp0_reserved: rproc@45000000 {
compatible = "shared-dma-pool";
reg = <0x45000000 0x00400000>;
no-map;
};
delta_reserved: rproc@44000000 {
compatible = "shared-dma-pool";
reg = <0x44000000 0x01000000>;
no-map;
};
};
cpus {
#address-cells = <1>;
#size-cells = <0>;
cpu0: cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-a9";
reg = <0>;
/* u-boot puts hpen in SBC dmem at 0xa4 offset */
cpu-release-addr = <0x94100A4>;
/* kHz uV */
operating-points = <1500000 0
1200000 0
800000 0
500000 0>;
clocks = <&clk_m_a9>;
clock-names = "cpu";
clock-latency = <100000>;
cpu0-supply = <&pwm_regulator>;
st,syscfg = <&syscfg_core 0x8e0>;
#cooling-cells = <2>;
};
cpu1: cpu@1 {
device_type = "cpu";
compatible = "arm,cortex-a9";
reg = <1>;
/* u-boot puts hpen in SBC dmem at 0xa4 offset */
cpu-release-addr = <0x94100A4>;
/* kHz uV */
operating-points = <1500000 0
1200000 0
800000 0
500000 0>;
#cooling-cells = <2>;
Annotation
- Immediate include surface: `stih407-pinctrl.dtsi`, `dt-bindings/mfd/st-lpc.h`, `dt-bindings/phy/phy.h`, `dt-bindings/reset/stih407-resets.h`, `dt-bindings/interrupt-controller/irq-st.h`.
- Atlas domain: Architecture Layer / arch/arm.
- Implementation status: atlas-only.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.