arch/arm/boot/dts/st/stih410.dtsi

Source file repositories/reference/linux-study-clean/arch/arm/boot/dts/st/stih410.dtsi

File Facts

System
Linux kernel
Corpus path
arch/arm/boot/dts/st/stih410.dtsi
Extension
.dtsi
Size
9972 bytes
Lines
382
Domain
Architecture Layer
Bucket
arch/arm
Inferred role
Architecture Layer: configuration, schema, or hardware description
Status
atlas-only

Why This File Exists

CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.

Dependency Surface

Detected Declarations

Annotated Snippet

// SPDX-License-Identifier: GPL-2.0-only
/*
 * Copyright (C) 2014 STMicroelectronics Limited.
 * Author: Peter Griffin <peter.griffin@linaro.org>
 */
#include "stih410-clock.dtsi"
#include "stih407-family.dtsi"
#include "stih410-pinctrl.dtsi"
#include <dt-bindings/gpio/gpio.h>
/ {
	aliases {
		bdisp0 = &bdisp0;
	};

	usb2_picophy1: phy2 {
		compatible = "st,stih407-usb2-phy";
		#phy-cells = <0>;
		st,syscfg = <&syscfg_core 0xf8 0xf4>;
		resets = <&softreset STIH407_PICOPHY_SOFTRESET>,
			 <&picophyreset STIH407_PICOPHY0_RESET>;
		reset-names = "global", "port";

		status = "disabled";
	};

	usb2_picophy2: phy3 {
		compatible = "st,stih407-usb2-phy";
		#phy-cells = <0>;
		st,syscfg = <&syscfg_core 0xfc 0xf4>;
		resets = <&softreset STIH407_PICOPHY_SOFTRESET>,
			 <&picophyreset STIH407_PICOPHY1_RESET>;
		reset-names = "global", "port";

		status = "disabled";
	};

	display-subsystem {
		compatible = "st,sti-display-subsystem";
		ports = <&compositor>, <&hqvdp>, <&tvout>, <&sti_hdmi>;

		assigned-clocks = <&clk_s_d2_quadfs 0>,
				  <&clk_s_d2_quadfs 1>,
				  <&clk_s_c0_pll1 0>,
				  <&clk_s_c0_flexgen CLK_COMPO_DVP>,
				  <&clk_s_c0_flexgen CLK_MAIN_DISP>,
				  <&clk_s_d2_flexgen CLK_PIX_MAIN_DISP>,
				  <&clk_s_d2_flexgen CLK_PIX_AUX_DISP>,
				  <&clk_s_d2_flexgen CLK_PIX_GDP1>,
				  <&clk_s_d2_flexgen CLK_PIX_GDP2>,
				  <&clk_s_d2_flexgen CLK_PIX_GDP3>,
				  <&clk_s_d2_flexgen CLK_PIX_GDP4>;

		assigned-clock-parents = <0>,
					 <0>,
					 <0>,
					 <&clk_s_c0_pll1 0>,
					 <&clk_s_c0_pll1 0>,
					 <&clk_s_d2_quadfs 0>,
					 <&clk_s_d2_quadfs 1>,
					 <&clk_s_d2_quadfs 0>,
					 <&clk_s_d2_quadfs 0>,
					 <&clk_s_d2_quadfs 0>,
					 <&clk_s_d2_quadfs 0>;

		assigned-clock-rates = <297000000>,
				       <297000000>,
				       <0>,
				       <400000000>,
				       <400000000>;
	};

Annotation

Implementation Notes