arch/arm/boot/dts/st/stih418.dtsi
Source file repositories/reference/linux-study-clean/arch/arm/boot/dts/st/stih418.dtsi
File Facts
- System
- Linux kernel
- Corpus path
arch/arm/boot/dts/st/stih418.dtsi- Extension
.dtsi- Size
- 4139 bytes
- Lines
- 155
- Domain
- Architecture Layer
- Bucket
- arch/arm
- Inferred role
- Architecture Layer: configuration, schema, or hardware description
- Status
- atlas-only
Why This File Exists
CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.
- CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.
Dependency Surface
stih418-clock.dtsistih407-family.dtsistih410-pinctrl.dtsidt-bindings/thermal/thermal.h
Detected Declarations
- No top-level syscall, struct, function, initcall, or export declaration detected by the generator.
Annotated Snippet
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (C) 2014 STMicroelectronics Limited.
* Author: Peter Griffin <peter.griffin@linaro.org>
*/
#include "stih418-clock.dtsi"
#include "stih407-family.dtsi"
#include "stih410-pinctrl.dtsi"
#include <dt-bindings/thermal/thermal.h>
/ {
cpus {
#address-cells = <1>;
#size-cells = <0>;
cpu2: cpu@2 {
device_type = "cpu";
compatible = "arm,cortex-a9";
reg = <2>;
/* u-boot puts hpen in SBC dmem at 0xa4 offset */
cpu-release-addr = <0x94100A4>;
#cooling-cells = <2>;
};
cpu3: cpu@3 {
device_type = "cpu";
compatible = "arm,cortex-a9";
reg = <3>;
/* u-boot puts hpen in SBC dmem at 0xa4 offset */
cpu-release-addr = <0x94100A4>;
#cooling-cells = <2>;
};
};
usb2_picophy1: phy2 {
compatible = "st,stih407-usb2-phy";
#phy-cells = <0>;
st,syscfg = <&syscfg_core 0xf8 0xf4>;
resets = <&softreset STIH407_PICOPHY_SOFTRESET>,
<&picophyreset STIH407_PICOPHY0_RESET>;
reset-names = "global", "port";
};
usb2_picophy2: phy3 {
compatible = "st,stih407-usb2-phy";
#phy-cells = <0>;
st,syscfg = <&syscfg_core 0xfc 0xf4>;
resets = <&softreset STIH407_PICOPHY_SOFTRESET>,
<&picophyreset STIH407_PICOPHY1_RESET>;
reset-names = "global", "port";
};
thermal-zones {
cpu_thermal: cpu-thermal {
polling-delay-passive = <250>; /* 250ms */
polling-delay = <1000>; /* 1000ms */
thermal-sensors = <&thermal>;
trips {
cpu_crit: cpu-crit {
temperature = <95000>; /* 95C */
hysteresis = <2000>;
type = "critical";
};
cpu_alert: cpu-alert {
temperature = <85000>; /* 85C */
hysteresis = <2000>;
type = "passive";
};
};
cooling-maps {
Annotation
- Immediate include surface: `stih418-clock.dtsi`, `stih407-family.dtsi`, `stih410-pinctrl.dtsi`, `dt-bindings/thermal/thermal.h`.
- Atlas domain: Architecture Layer / arch/arm.
- Implementation status: atlas-only.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.