arch/arm/boot/dts/st/stm32mp131.dtsi
Source file repositories/reference/linux-study-clean/arch/arm/boot/dts/st/stm32mp131.dtsi
File Facts
- System
- Linux kernel
- Corpus path
arch/arm/boot/dts/st/stm32mp131.dtsi- Extension
.dtsi- Size
- 47786 bytes
- Lines
- 1923
- Domain
- Architecture Layer
- Bucket
- arch/arm
- Inferred role
- Architecture Layer: configuration, schema, or hardware description
- Status
- atlas-only
Why This File Exists
CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.
- CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.
Dependency Surface
dt-bindings/arm/coresight-cti-dt.hdt-bindings/interrupt-controller/arm-gic.hdt-bindings/clock/stm32mp13-clks.hdt-bindings/reset/stm32mp13-resets.h
Detected Declarations
- No top-level syscall, struct, function, initcall, or export declaration detected by the generator.
Annotated Snippet
// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
/*
* Copyright (C) STMicroelectronics 2021 - All Rights Reserved
* Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics.
*/
#include <dt-bindings/arm/coresight-cti-dt.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/clock/stm32mp13-clks.h>
#include <dt-bindings/reset/stm32mp13-resets.h>
/ {
#address-cells = <1>;
#size-cells = <1>;
cpus {
#address-cells = <1>;
#size-cells = <0>;
cpu0: cpu@0 {
compatible = "arm,cortex-a7";
device_type = "cpu";
reg = <0>;
};
};
arm-pmu {
compatible = "arm,cortex-a7-pmu";
interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
interrupt-affinity = <&cpu0>;
interrupt-parent = <&intc>;
};
arm_wdt: watchdog {
compatible = "arm,smc-wdt";
arm,smc-id = <0xbc000000>;
status = "disabled";
};
firmware {
optee {
method = "smc";
compatible = "linaro,optee-tz";
interrupt-parent = <&intc>;
interrupts = <GIC_PPI 15 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>;
};
scmi: scmi {
compatible = "linaro,scmi-optee";
#address-cells = <1>;
#size-cells = <0>;
linaro,optee-channel-id = <0>;
scmi_clk: protocol@14 {
reg = <0x14>;
#clock-cells = <1>;
};
scmi_reset: protocol@16 {
reg = <0x16>;
#reset-cells = <1>;
};
scmi_voltd: protocol@17 {
reg = <0x17>;
scmi_regu: regulators {
#address-cells = <1>;
#size-cells = <0>;
scmi_reg11: regulator@0 {
Annotation
- Immediate include surface: `dt-bindings/arm/coresight-cti-dt.h`, `dt-bindings/interrupt-controller/arm-gic.h`, `dt-bindings/clock/stm32mp13-clks.h`, `dt-bindings/reset/stm32mp13-resets.h`.
- Atlas domain: Architecture Layer / arch/arm.
- Implementation status: atlas-only.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.