arch/arm/boot/dts/ti/omap/am3874-iceboard.dts

Source file repositories/reference/linux-study-clean/arch/arm/boot/dts/ti/omap/am3874-iceboard.dts

File Facts

System
Linux kernel
Corpus path
arch/arm/boot/dts/ti/omap/am3874-iceboard.dts
Extension
.dts
Size
13772 bytes
Lines
490
Domain
Architecture Layer
Bucket
arch/arm
Inferred role
Architecture Layer: configuration, schema, or hardware description
Status
atlas-only

Why This File Exists

CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.

Dependency Surface

Detected Declarations

Annotated Snippet

// SPDX-License-Identifier: GPL-2.0
/*
 * Device tree for Winterland IceBoard
 *
 * https://mcgillcosmology.com
 * https://threespeedlogic.com
 *
 * This is an ARM + FPGA instrumentation board used at telescopes in
 * Antarctica (the South Pole Telescope), Chile (POLARBEAR), and at the DRAO
 * observatory in British Columbia (CHIME).
 *
 * Copyright (c) 2019 Three-Speed Logic, Inc. <gsmecher@threespeedlogic.com>
 */

/dts-v1/;

#include "dm814x.dtsi"
#include <dt-bindings/interrupt-controller/irq.h>

/ {
	model = "Winterland IceBoard";
	compatible = "ti,dm8148", "ti,dm814";

	chosen {
		stdout-path = "serial1:115200n8";
		bootargs = "earlycon";
	};

	memory@80000000 {
		device_type = "memory";
		reg = <0x80000000 0x40000000>;	/* 1 GB */
	};

	vmmcsd_fixed: fixedregulator0 {
		compatible = "regulator-fixed";
		regulator-name = "vmmcsd_fixed";
		regulator-min-microvolt = <3300000>;
		regulator-max-microvolt = <3300000>;
		regulator-always-on;
	};
};

/* The MAC provides internal delay for the transmit path ONLY, which is enabled
 * provided no -id/-txid/-rxid suffix is provided to "phy-mode".
 *
 * The receive path is delayed at the PHY. The recommended register settings
 * are 0xf0 for the control bits, and 0x7777 for the data bits. However, the
 * conversion code in the kernel lies: the PHY's registers are 120 ps per tap,
 * and the kernel assumes 200 ps per tap. So we have fudged the numbers here to
 * obtain the correct register settings.
 */
&mac { dual_emac = <1>; };
&cpsw_emac0 {
	phy-handle = <&ethphy0>;
	phy-mode = "rgmii";
	dual_emac_res_vlan = <1>;
};
&cpsw_emac1 {
	phy-handle = <&ethphy1>;
	phy-mode = "rgmii";
	dual_emac_res_vlan = <2>;
};

&davinci_mdio {
	ethphy0: ethernet-phy@0 {
		reg = <0x2>;

		rxc-skew-ps = <3000>;
		rxdv-skew-ps = <0>;

Annotation

Implementation Notes