arch/arm/boot/dts/ti/omap/dra7-ipu-dsp-common.dtsi

File Facts

System

Linux kernel

Corpus path

arch/arm/boot/dts/ti/omap/dra7-ipu-dsp-common.dtsi

Extension

.dtsi

Size

697 bytes

Lines

40

Domain

Architecture Layer

Bucket

arch/arm

Inferred role

Architecture Layer: configuration, schema, or hardware description

Status

atlas-only

Why This File Exists

CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.

• CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.

Dependency Surface

• No C-style include directives detected by the generator.

Detected Declarations

• No top-level syscall, struct, function, initcall, or export declaration detected by the generator.

Annotated Snippet

// SPDX-License-Identifier: GPL-2.0
/*
 * Common IPU and DSP data for TI DRA7xx/AM57xx platforms
 */

&mailbox5 {
	status = "okay";
	mbox_ipu1_ipc3x: mbox-ipu1-ipc3x {
		status = "okay";
	};
	mbox_dsp1_ipc3x: mbox-dsp1-ipc3x {
		status = "okay";
	};
};

&mailbox6 {
	status = "okay";
	mbox_ipu2_ipc3x: mbox-ipu2-ipc3x {
		status = "okay";
	};
};

&ipu2 {
	mboxes = <&mailbox6 &mbox_ipu2_ipc3x>;
	ti,timers = <&timer3>;
	ti,watchdog-timers = <&timer4>, <&timer9>;
};

&ipu1 {
	mboxes = <&mailbox5 &mbox_ipu1_ipc3x>;
	ti,timers = <&timer11>;
	ti,watchdog-timers = <&timer7>, <&timer8>;
};

&dsp1 {
	mboxes = <&mailbox5 &mbox_dsp1_ipc3x>;
	ti,timers = <&timer5>;
	ti,watchdog-timers = <&timer10>;
};

Annotation

• Atlas domain: Architecture Layer / arch/arm.
• Implementation status: atlas-only.

Implementation Notes

• This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
• Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
• Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.