arch/arm/boot/dts/ti/omap/logicpd-som-lv-baseboard.dtsi
Source file repositories/reference/linux-study-clean/arch/arm/boot/dts/ti/omap/logicpd-som-lv-baseboard.dtsi
File Facts
- System
- Linux kernel
- Corpus path
arch/arm/boot/dts/ti/omap/logicpd-som-lv-baseboard.dtsi- Extension
.dtsi- Size
- 7288 bytes
- Lines
- 238
- Domain
- Architecture Layer
- Bucket
- arch/arm
- Inferred role
- Architecture Layer: configuration, schema, or hardware description
- Status
- atlas-only
Why This File Exists
CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.
- CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.
Dependency Surface
- No C-style include directives detected by the generator.
Detected Declarations
- No top-level syscall, struct, function, initcall, or export declaration detected by the generator.
Annotated Snippet
// SPDX-License-Identifier: GPL-2.0-only
/ {
gpio_keys {
compatible = "gpio-keys";
pinctrl-names = "default";
pinctrl-0 = <&gpio_key_pins>;
sysboot2 {
label = "gpio3";
gpios = <&gpio4 15 GPIO_ACTIVE_LOW>; /* gpio_111 / uP_GPIO_3 */
linux,code = <BTN_0>;
wakeup-source;
};
};
sound {
compatible = "ti,omap-twl4030";
ti,model = "omap3logic";
ti,mcbsp = <&mcbsp2>;
};
leds {
compatible = "gpio-leds";
pinctrl-names = "default";
pinctrl-0 = <&led_pins &led_pins_wkup>;
led1 {
label = "led1";
gpios = <&gpio5 5 GPIO_ACTIVE_LOW>; /* gpio133 */
linux,default-trigger = "cpu0";
};
led2 {
label = "led2";
gpios = <&gpio1 11 GPIO_ACTIVE_LOW>; /* gpio11 */
linux,default-trigger = "none";
};
};
};
&vaux1 {
regulator-min-microvolt = <3000000>;
regulator-max-microvolt = <3000000>;
};
&vaux4 {
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
};
&mcbsp2 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&mcbsp2_pins>;
};
&charger {
ti,bb-uvolt = <3200000>;
ti,bb-uamp = <150>;
};
&gpmc {
ranges = <0 0 0x30000000 0x1000000 /* CS0: 16MB for NAND */
1 0 0x2c000000 0x1000000 /* CS1: 16MB for LAN9221 */
2 0 0x10000000 0x2000000>; /* CS2: 32MB for NOR */
ethernet@gpmc {
pinctrl-names = "default";
pinctrl-0 = <&lan9221_pins>;
Annotation
- Atlas domain: Architecture Layer / arch/arm.
- Implementation status: atlas-only.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.