arch/arm/boot/dts/ti/omap/omap5.dtsi
Source file repositories/reference/linux-study-clean/arch/arm/boot/dts/ti/omap/omap5.dtsi
File Facts
- System
- Linux kernel
- Corpus path
arch/arm/boot/dts/ti/omap/omap5.dtsi- Extension
.dtsi- Size
- 21413 bytes
- Lines
- 833
- Domain
- Architecture Layer
- Bucket
- arch/arm
- Inferred role
- Architecture Layer: exported/initcall integration point
- Status
- integration implementation candidate
Why This File Exists
CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.
- CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.
- Exports symbols or registers init work; inspect boot/module ordering and who consumes the exported contract.
Dependency Surface
dt-bindings/bus/ti-sysc.hdt-bindings/gpio/gpio.hdt-bindings/interrupt-controller/arm-gic.hdt-bindings/pinctrl/omap.hdt-bindings/clock/omap5.homap4-cpu-thermal.dtsiomap5-gpu-thermal.dtsiomap5-core-thermal.dtsiomap5-l4.dtsiomap54xx-clocks.dtsiomap5-l4-abe.dtsi
Detected Declarations
- No top-level syscall, struct, function, initcall, or export declaration detected by the generator.
Annotated Snippet
* interconnect as simple-pm-bus probes at module_init() time.
*/
ocmcram: sram@40300000 {
compatible = "mmio-sram";
reg = <0 0x40300000 0 0x20000>; /* 128k */
};
gic: interrupt-controller@48211000 {
compatible = "arm,cortex-a15-gic";
interrupt-controller;
#interrupt-cells = <3>;
reg = <0 0x48211000 0 0x1000>,
<0 0x48212000 0 0x2000>,
<0 0x48214000 0 0x2000>,
<0 0x48216000 0 0x2000>;
interrupt-parent = <&gic>;
};
wakeupgen: interrupt-controller@48281000 {
compatible = "ti,omap5-wugen-mpu", "ti,omap4-wugen-mpu";
interrupt-controller;
#interrupt-cells = <3>;
reg = <0 0x48281000 0 0x1000>;
interrupt-parent = <&gic>;
};
/*
* XXX: Use a flat representation of the OMAP3 interconnect.
* The real OMAP interconnect network is quite complex.
* Since it will not bring real advantage to represent that in DT for
* the moment, just use a fake OCP bus entry to represent the whole bus
* hierarchy.
*/
ocp {
compatible = "simple-pm-bus";
power-domains = <&prm_core>;
clocks = <&l3main1_clkctrl OMAP5_L3_MAIN_1_CLKCTRL 0>,
<&l3main2_clkctrl OMAP5_L3_MAIN_2_CLKCTRL 0>,
<&l3instr_clkctrl OMAP5_L3_MAIN_3_CLKCTRL 0>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0 0 0xc0000000>;
dma-ranges = <0x80000000 0x0 0x80000000 0x80000000>;
l3-noc@44000000 {
compatible = "ti,omap5-l3-noc";
reg = <0x44000000 0x2000>,
<0x44800000 0x3000>,
<0x45000000 0x4000>;
interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
};
l4_wkup: interconnect@4ae00000 {
};
l4_cfg: interconnect@4a000000 {
};
l4_per: interconnect@48000000 {
};
target-module@48210000 {
compatible = "ti,sysc-omap4-simple", "ti,sysc";
power-domains = <&prm_mpu>;
clocks = <&mpu_clkctrl OMAP5_MPU_CLKCTRL 0>;
clock-names = "fck";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x48210000 0x1f0000>;
Annotation
- Immediate include surface: `dt-bindings/bus/ti-sysc.h`, `dt-bindings/gpio/gpio.h`, `dt-bindings/interrupt-controller/arm-gic.h`, `dt-bindings/pinctrl/omap.h`, `dt-bindings/clock/omap5.h`, `omap4-cpu-thermal.dtsi`, `omap5-gpu-thermal.dtsi`, `omap5-core-thermal.dtsi`.
- Atlas domain: Architecture Layer / arch/arm.
- Implementation status: integration implementation candidate.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.