arch/arm/boot/dts/ti/omap/omap5-gpu-thermal.dtsi

File Facts

System

Linux kernel

Corpus path

arch/arm/boot/dts/ti/omap/omap5-gpu-thermal.dtsi

Extension

.dtsi

Size

615 bytes

Lines

26

Domain

Architecture Layer

Bucket

arch/arm

Inferred role

Architecture Layer: configuration, schema, or hardware description

Status

atlas-only

Why This File Exists

CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.

• CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.

Dependency Surface

• dt-bindings/thermal/thermal.h

Detected Declarations

• No top-level syscall, struct, function, initcall, or export declaration detected by the generator.

Annotated Snippet

// SPDX-License-Identifier: GPL-2.0-only
/*
 * Device Tree Source for OMAP543x SoC GPU thermal
 *
 * Copyright (C) 2013 Texas Instruments Incorporated - https://www.ti.com/
 * Contact: Eduardo Valentin <eduardo.valentin@ti.com>
 */

#include <dt-bindings/thermal/thermal.h>

gpu_thermal: gpu_thermal {
	polling-delay-passive = <250>; /* milliseconds */
	polling-delay = <500>; /* milliseconds */

			/* sensor       ID */
	thermal-sensors = <&bandgap     1>;

	trips {
		gpu_crit: gpu_crit {
			temperature = <125000>; /* milliCelsius */
			hysteresis = <2000>; /* milliCelsius */
			type = "critical";
		};
	};
};

Annotation

• Immediate include surface: `dt-bindings/thermal/thermal.h`.
• Atlas domain: Architecture Layer / arch/arm.
• Implementation status: atlas-only.

Implementation Notes

• This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
• Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
• Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.