arch/arm/common/secure_cntvoff.S
Source file repositories/reference/linux-study-clean/arch/arm/common/secure_cntvoff.S
File Facts
- System
- Linux kernel
- Corpus path
arch/arm/common/secure_cntvoff.S- Extension
.S- Size
- 825 bytes
- Lines
- 33
- Domain
- Architecture Layer
- Bucket
- arch/arm
- Inferred role
- Architecture Layer: arch/arm
- Status
- atlas-only
Why This File Exists
CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.
- CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.
Dependency Surface
linux/linkage.hasm/assembler.h
Detected Declarations
- No top-level syscall, struct, function, initcall, or export declaration detected by the generator.
Annotated Snippet
#include <linux/linkage.h>
#include <asm/assembler.h>
ENTRY(secure_cntvoff_init)
.arch armv7-a
/*
* CNTVOFF has to be initialized either from non-secure Hypervisor
* mode or secure Monitor mode with SCR.NS==1. If TrustZone is enabled
* then it should be handled by the secure code. The CPU must implement
* the virtualization extensions.
*/
cps #MON_MODE
mrc p15, 0, r1, c1, c1, 0 /* Get Secure Config */
orr r0, r1, #1
mcr p15, 0, r0, c1, c1, 0 /* Set Non Secure bit */
isb
mov r0, #0
mcrr p15, 4, r0, r0, c14 /* CNTVOFF = 0 */
isb
mcr p15, 0, r1, c1, c1, 0 /* Set Secure bit */
isb
cps #SVC_MODE
ret lr
ENDPROC(secure_cntvoff_init)
Annotation
- Immediate include surface: `linux/linkage.h`, `asm/assembler.h`.
- Atlas domain: Architecture Layer / arch/arm.
- Implementation status: atlas-only.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.